From: Marcel Ziswiler <marcel.ziswi...@toradex.com> Fix second mux option of clkout0 which should really be DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK10 rather than twice the same according to [1].
[1] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html#clocks-for-board0-device Signed-off-by: Marcel Ziswiler <marcel.ziswi...@toradex.com> Reviewed-by: Bryan Brattlof <b...@ti.com> --- (no changes since v2) Changes in v2: - Add Bryan's reviewed-by tag. Thanks! arch/arm/mach-k3/am62x/clk-data.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/am62x/clk-data.c index c0881778fe7..d7bfed0e031 100644 --- a/arch/arm/mach-k3/am62x/clk-data.c +++ b/arch/arm/mach-k3/am62x/clk-data.c @@ -57,7 +57,7 @@ static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk10", }; static const char * const clk_32k_rc_sel_out0_parents[] = { @@ -195,6 +195,7 @@ static const struct clk_data clk_list[] = { CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), @@ -313,7 +314,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 20, "clkout0_ctrl_out0"), DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"), DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 25, "board_0_ddr0_ck0_out"), DEV_CLK(157, 40, "mshsi2c_main_0_porscl"), -- 2.36.1
