From: Steffen Dirkwinkel <s.dirkwin...@beckhoff.com> We need it for coherent access between pl and ps.
>From xilinx documentation: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842098/Zynq+UltraScale+MPSoC+Cache+Coherency Inner Cache Broadcasting Linux sets up the MMU for cacheable memory to be inner shareable as that supports SMP operation. As modifying the MMU tables from kernel or userspace is not a straightforwards task, the inner cache broadcasting feature can be used to allow inner cacheble transactions be broadcasted. Outside the APU, in the outer domain, the CCI handles coherency across the system. The brdc_inner bit of the lpd_apu register within the LPD_SLCR module must be written while the APU is in reset. The requirement to alter the register while the APU is in reset can be accomplished using the register initialization feature in the boot image. .set. 0xFF41A040 = 0x3; Signed-off-by: Steffen Dirkwinkel <s.dirkwin...@beckhoff.com> --- board/xilinx/zynqmp/zynqmp-beckhoff-cx8200/regs.init | 1 + 1 file changed, 1 insertion(+) create mode 100644 board/xilinx/zynqmp/zynqmp-beckhoff-cx8200/regs.init diff --git a/board/xilinx/zynqmp/zynqmp-beckhoff-cx8200/regs.init b/board/xilinx/zynqmp/zynqmp-beckhoff-cx8200/regs.init new file mode 100644 index 0000000000..e7038dd80a --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-beckhoff-cx8200/regs.init @@ -0,0 +1 @@ +0xFF41A040 0x3 \ No newline at end of file -- 2.42.0
