commit 7355ad1950f41e755e6dc451834be3b94f82acd4 Linux upstream. Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The chip contains two CAN peripherals, CAN1 the primary and CAN2 the secondary, that share some of the required logic like clock and filters. This means that the secondary CAN can't be used without the primary CAN.
Signed-off-by: Dario Binacchi <dario.binac...@amarulasolutions.com> Link: https://lore.kernel.org/all/20230328073328.3949796-4-dario.binac...@amarulasolutions.com Signed-off-by: Marc Kleine-Budde <m...@pengutronix.de> --- arch/arm/dts/stm32f429.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi index e5b13aca40c0..22225104fca8 100644 --- a/arch/arm/dts/stm32f429.dtsi +++ b/arch/arm/dts/stm32f429.dtsi @@ -321,6 +321,35 @@ status = "disabled"; }; + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-primary; + st,gcan = <&gcan>; + status = "disabled"; + }; + + gcan: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + st,gcan = <&gcan>; + status = "disabled"; + }; + dac: dac@40007400 { compatible = "st,stm32f4-dac-core"; reg = <0x40007400 0x400>; -- 2.34.1
