Re: [PATCH v2 2/5] clk: rk3588: Add 742.5M parameter for PLL

[Kever Yang]

On 2023/10/11 18:29, Elaine Zhang wrote:

From: Guochun Huang <hero.hu...@rock-chips.com>

For a specific frequency.

Signed-off-by: Guochun Huang <hero.hu...@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangq...@rock-chips.com>

Reviewed-by: Kever Yang <kever.y...@rock-chips.com>

Thanks,
- Kever

---
  drivers/clk/rockchip/clk_rk3588.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk_rk3588.c 
b/drivers/clk/rockchip/clk_rk3588.c
index 119b1337bdf2..c86176264147 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -36,6 +36,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
        RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
        RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
        RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
+       RK3588_PLL_RATE(742500000, 4, 495, 2, 0),
        RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
        RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
        RK3588_PLL_RATE(594000000, 2, 198, 2, 0),