On 10/9/23 18:46, Paul Barker wrote:
This driver provides clock and reset control for the Renesas R9A07G044L (RZ/G2L) and R9A07G044C (RZ/G2LC) SoC. It consists of two parts:* driver code which is applicable to all SoCs in the RZ/G2L family. * static data describing the clocks and resets which are specific to the R9A07G044{L,C} SoCs. The identifier r9a07g044 (without a final letter) is used to indicate that both SoCs are supported. clk_set_rate() and clk_get_rate() are implemented only for the clocks that are actually used in u-boot. The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind function is called before the SCIF (serial port) driver is probed. This is required so that we can de-assert the relevant reset signal during the serial driver probe function. This patch is based on the corresponding Linux v6.5 driver (commit 52e12027d50affbf60c6c9c64db8017391b0c22e). Signed-off-by: Paul Barker <paul.barker...@bp.renesas.com> Reviewed-by: Biju Das <biju.das...@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+rene...@mailbox.org>
