From: Gunjan Gupta <viran...@gmail.com>
During the DRAM controller setup, we program its registers for certain
configurations (multiple times), then try to access the DRAM array, to
detect the number of rows and columns in the used DRAM chips.
This requires that all MMIO writes have reached the DRAM controller,
before we actually access the DRAM.
Add a DSB instruction at the end of the controller init function, that
ensures that outstanding stores have been completed.
That hopefully fixes occasional DRAM init failures on some H6 boards
like the Orange Pi 3 LTS, where this leads to the erroneous detection of
4GB instead of the actual 2GB.
Signed-off-by: Gunjan Gupta <viran...@gmail.com>
[Andre: move DSB, add comment]
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm/mach-sunxi/dram_sun50i_h6.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c
b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index bff2e42513c..43a2d19f084 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -554,6 +554,12 @@ static bool mctl_channel_init(struct dram_para *para)
writel(0x7ff, &mctl_com->maer1);
writel(0xffff, &mctl_com->maer2);
+ /*
+ * Make sure all MMIO writes are committed to the DRAM controller,
+ * so that accesses to the DRAM array adhere to the above programming.
+ */
+ dsb();
+
return true;
}
--
2.35.8
