On Thu, Nov 09, 2023 at 11:43:12AM +0100, Thomas Richard wrote: > On 11/7/23 19:18, Tom Rini wrote: > > On Tue, Nov 07, 2023 at 05:18:00PM +0100, Thomas Richard wrote: > > > >> Add the board specific part of the exit retention sequence for k3-ddrss > >> > >> Based on the work of Gregory CLEMENT <gregory.clem...@bootlin.com> > >> > >> Signed-off-by: Thomas Richard <thomas.rich...@bootlin.com> > >> Signed-off-by: Gregory CLEMENT <gregory.clem...@bootlin.com> > > > > If this ends up being physical board design specific and so someone > > making a new design for this SoC with a custom board layout entirely > > needs something else, we should think harder about what's in > > board_is_resuming() vs what we document the function does. If however, > > this is generic to the SoC and will be needed, it should be folded in > > with the previous patch and the commit message expanded, and the > > documentation part of this series explain clearly what the functions are > > responsible for. > > > > Hi Tom, > > Thanks for all these interesting feedback's. > > From my point of view, board_is_resuming will work with all j7* SoCs and > all new designs for these SoCs. > This function only read and erase a scratchpad register in the PMIC A. > So it should be ok for all designs which have the PMIC@48. > > For the function board_k3_ddrss_lpddr4_release_retention, it's a little > bit more tricky. The sequence is specific to the SOC, but the GPIOs used > are specific to the board.
I suspect this is going to be the case where a judgement call will have to be made on theory vs practical on if the GPIOs will be duplicated to custom designs (it's tricky! TI gave us a working solution, just use it!) or changed based on other needs. I'll hope that perhaps people know who to talk with in-private to get some unofficial feedback on such things. -- Tom
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