On Sat, Nov 25, 2023 at 01:16:05PM +0200, Roger Quadros wrote:
> AM335x uses a special driver "am335x_spl_bch.c" as SPL
> NAND loader. This driver expects 1 sector at a time ECC
> and doesn't work well with multi-sector ECC that was implemented in
> commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> correction")
>
> Switch back to 1 sector at a time read/ECC.
>
> Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based
> correction")
> Signed-off-by: Roger Quadros <rog...@kernel.org>
> ---
> drivers/mtd/nand/raw/omap_gpmc.c | 95 ++++++++++----------------------
> 1 file changed, 29 insertions(+), 66 deletions(-)I'm glad to see this fixed. My question is, can we abstract this slightly as I assume there's a performance hit on the newer SoCs that support more than one sector at a time for ECC and I assume it's just am335x and related that don't support the feature. Thanks. -- Tom
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