> -----Original Message----- > From: Richard Retanubun [mailto:richardretanu...@ruggedcom.com] > Sent: Thursday, February 03, 2011 11:50 PM > To: u-boot@lists.denx.de > Cc: Jin Zhengxiong-R64188; Richard Retanubun > Subject: [PATCH 1/3] ColdFire: Queued SPI driver > > This patch adds a driver for Freescale Colfire Queued SPI bus. > Coded to work with 8 bits per transfer to use with SPI flash. > CPOL, CPHA, and CS_ACTIVE_HIGH can be configured. > > Tested with MCF5270 which have 4 chip selects. > > Activate by #define CONFIG_CF_QSPI in board config. > --- > arch/m68k/cpu/mcf52x2/cpu_init.c | 134 +++++++++++++++++- > arch/m68k/include/asm/coldfire/qspi.h | 2 +- > arch/m68k/include/asm/m5271.h | 26 ++++ > drivers/spi/Makefile | 1 + > drivers/spi/cf_qspi.c | 257 > +++++++++++++++++++++++++++++++++ > 5 files changed, 418 insertions(+), 2 deletions(-) > create mode 100644 drivers/spi/cf_qspi.c > Some general comments, thanks. Please try the checkpatch script to clean up most of the errors and warnings.
Current DSPI code works as PIO mode. So please try to merge the qspi code to the current cf_spi code, and please unify the register access. Only put the critical config in the cpu_init.c, please try to move the cs_activate and cs_deactivate to the spi driver. Please clean up the Copyright information, Remove the Motorola information. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
