[PATCH 01/12] clk: renesas: Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.6.3

[Marek Vasut]

Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 
6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Add ZG clock macro into rcar-gen3-cpg.h to cover the new clock type .

Signed-off-by: Marek Vasut <marek.vasut+rene...@mailbox.org>
---
 drivers/clk/renesas/r8a7796-cpg-mssr.c | 3 +++
 drivers/clk/renesas/rcar-gen3-cpg.h    | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index ea1f6d69062..d741d547ec8 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -80,6 +80,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] 
__initconst = {
        /* Core Clock Outputs */
        DEF_GEN3_Z("z",         R8A7796_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 
2, 8),
        DEF_GEN3_Z("z2",        R8A7796_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 
2, 0),
+       DEF_GEN3_Z("zg",        R8A7796_CLK_ZG,    CLK_TYPE_GEN3_ZG, CLK_PLL4, 
4, 24),
        DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
        DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -129,6 +130,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] 
__initconst = {
 };
 
 static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
+       DEF_MOD("3dge",                  112,   R8A7796_CLK_ZG),
        DEF_MOD("fdp1-0",                119,   R8A7796_CLK_S0D1),
        DEF_MOD("tmu4",                  121,   R8A7796_CLK_S0D6),
        DEF_MOD("tmu3",                  122,   R8A7796_CLK_S3D2),
@@ -235,6 +237,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
        DEF_MOD("rpc-if",                917,   R8A7796_CLK_RPCD2),
        DEF_MOD("i2c6",                  918,   R8A7796_CLK_S0D6),
        DEF_MOD("i2c5",                  919,   R8A7796_CLK_S0D6),
+       DEF_MOD("adg",                   922,   R8A7796_CLK_S0D4),
        DEF_MOD("i2c-dvfs",              926,   R8A7796_CLK_CP),
        DEF_MOD("i2c4",                  927,   R8A7796_CLK_S0D6),
        DEF_MOD("i2c3",                  928,   R8A7796_CLK_S0D6),
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h 
b/drivers/clk/renesas/rcar-gen3-cpg.h
index 06318c81acd..370f26c4f0f 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -24,6 +24,7 @@ enum rcar_gen3_clk_types {
        CLK_TYPE_GEN3_R,
        CLK_TYPE_GEN3_MDSEL,    /* Select parent/divider using mode pin */
        CLK_TYPE_GEN3_Z,
+       CLK_TYPE_GEN3_ZG,
        CLK_TYPE_GEN3_OSC,      /* OSC EXTAL predivider and fixed divider */
        CLK_TYPE_GEN3_RCKSEL,   /* Select parent/divider using RCKCR.CKSEL */
        CLK_TYPE_GEN3_RPCSRC,
-- 
2.42.0