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MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatible with classic MicroBlaze processor.
The patch contains initial wiring and configuration for initial HW
design
with memory, cpu, interrupt controller, timers and uartlite console
(interrupt controller is listed but U-Boot is not using it).
Provided DT is just describing one configuration and should be taken
only
as example.
Signed-off-by: Michal Simek <michal.si...@amd.com>
---
Changes in v2:
- Extend commit message
- DT changes, add interrupt controller, check agains dt schema
- The patch for amd,mbv32 compatible string is here
https://lore.kernel.org/r/d442d916204d26f82c1c3a924a4cdfb117960e1b.1699270661.git.michal.si...@amd.com
- The patch for board compatibility is here
https://lore.kernel.org/r/50c277c92c41a582ef171fb75efc6a6a4f860be2.1699271616.git.michal.si...@amd.com
xlnx,xps-intc-1.00.a driver exists in the Linux kernel but DT binding
is
missing. That's something what we need to work on.
arch/arm64/boot/dts/xilinx/xilinx-mbv32.dtb:
/axi/interrupt-controller@41200000: failed to match any schema with
compatible: ['xlnx,xps-intc-1.00.a']
Public annoucement is available here if someone is interested.
https://www.xilinx.com/products/design-tools/microblaze-v.html?utm_source=marketo&utm_medium=email&utm_campaign=EN-EM-2023-11-02-New-MicroBlaze-V-Processor&utm_term=btn&mkt_tok=NDA5LVdZWC03MjQAAAGPMMJYuPPscCags7WdvOeUSWy-_mC9aOwrobFaZRf5ok_eHoQUvTLBzJdHrkcBId9tQ4a-odfnU91WjUkIxx-iSG4OKGofjK5iZcAiK_VN8_xK
---
arch/riscv/Kconfig | 4 +
arch/riscv/dts/Makefile | 2 +
arch/riscv/dts/xilinx-mbv32.dts | 106
+++++++++++++++++++++++++++
board/xilinx/Kconfig | 3 +-
board/xilinx/common/board.c | 5 ++
board/xilinx/mbv/Kconfig | 28 +++++++
board/xilinx/mbv/MAINTAINERS | 7 ++
board/xilinx/mbv/Makefile | 5 ++
board/xilinx/mbv/board.c | 11 +++
configs/xilinx_mbv32_defconfig | 30 ++++++++
configs/xilinx_mbv32_smode_defconfig | 32 ++++++++
include/configs/xilinx_mbv.h | 6 ++
12 files changed, 238 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/dts/xilinx-mbv32.dts
create mode 100644 board/xilinx/mbv/Kconfig
create mode 100644 board/xilinx/mbv/MAINTAINERS
create mode 100644 board/xilinx/mbv/Makefile
create mode 100644 board/xilinx/mbv/board.c
create mode 100644 configs/xilinx_mbv32_defconfig
create mode 100644 configs/xilinx_mbv32_smode_defconfig
create mode 100644 include/configs/xilinx_mbv.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6d0d812ddb55..67126d96af89 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -39,6 +39,9 @@ config TARGET_TH1520_LPI4A
bool "Support Sipeed's TH1520 Lichee PI 4A Board"
select SYS_CACHE_SHIFT_6
+config TARGET_XILINX_MBV
+ bool "Support AMD/Xilinx MicroBlaze V"
+
endchoice
config SYS_ICACHE_OFF
@@ -82,6 +85,7 @@ source "board/sifive/unmatched/Kconfig"
source "board/sipeed/maix/Kconfig"
source "board/starfive/visionfive2/Kconfig"
source "board/thead/th1520_lpi4a/Kconfig"
+source "board/xilinx/mbv/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/andesv5/Kconfig"
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index be6c8a422729..b05bb5607f06 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -9,6 +9,8 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-
unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-
visionfive-2.dtb
dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
+dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
+
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-
mbv32.dts
new file mode 100644
index 000000000000..6a6b8b694bd1
--- /dev/null
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for AMD MicroBlaze V
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.si...@amd.com>
+ */
+
+/dts-v1/;
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "AMD MicroBlaze V 32bit";
+ compatible = "amd,mbv";
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <102000000>;
+ cpu_0: cpu@0 {
+ compatible = "amd,mbv32", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ riscv,isa = "rv32imafdc";
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ clock-frequency = <102000000>;
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@20000000 {
+ device_type = "memory";
+ reg = <0x20000000 0x20000000>;
+ };
+
+ clk102: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <102000000>;
+ };
+
+ axi: axi {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+ bootph-all;
+
+ axi_intc: interrupt-controller@41200000 {
+ compatible = "xlnx,xps-intc-1.00.a";
+ reg = <0x41200000 0x1000>;
+ interrupt-controller;
+ interrupt-parent = <&cpu0_intc>;
+ #interrupt-cells = <2>;
+ kind-of-intr = <0>;
+ };
+
+ xlnx_timer0: timer@41c00000 {
+ compatible = "xlnx,xps-timer-1.00.a";
+ reg = <0x41c00000 0x1000>;
+ interrupt-parent = <&axi_intc>;
+ interrupts = <1 2>;
+ bootph-all;
+ xlnx,one-timer-only = <0>;
+ clock-names = "s_axi_aclk";
+ clocks = <&clk102>;
+ };
+
+ xlnx_timer1: timer@41c20000 {
+ compatible = "xlnx,xps-timer-1.00.a";
+ reg = <0x41c20000 0x1000>;
+ interrupt-parent = <&axi_intc>;
+ interrupts = <0 2>;
+ xlnx,one-timer-only = <0>;
+ clock-names = "s_axi_aclk";
+ clocks = <&clk102>;
+ };
+
+ uart0: serial@40600000 {
+ compatible = "xlnx,xps-uartlite-1.00.a";
+ reg = <0x40600000 0x1000>;
+ interrupt-parent = <&axi_intc>;
+ interrupts = <2 2>;
+ bootph-all;
+ clocks = <&clk102>;
+ current-speed = <115200>;
+ xlnx,data-bits = <8>;
+ xlnx,use-parity = <0>;
+ };
+ };
+};
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index 4f0776e8bd95..843198fa0da8 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -51,10 +51,11 @@ config XILINX_OF_BOARD_DTB_ADDR
config BOOT_SCRIPT_OFFSET
hex "Boot script offset"
- depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL ||
ARCH_VERSAL_NET || MICROBLAZE
+ depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL ||
ARCH_VERSAL_NET || MICROBLAZE || TARGET_XILINX_MBV
default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE
default 0x3E80000 if ARCH_ZYNQMP
default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET
+ default 0 if TARGET_XILINX_MBV
help
Specifies distro boot script offset in NAND/QSPI/NOR
flash.
diff --git a/board/xilinx/common/board.c
b/board/xilinx/common/board.c
index 9309b071269f..12a877c71549 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -652,6 +652,11 @@ int embedded_dtb_select(void)
#endif
#if defined(CONFIG_LMB)
+
+#ifndef MMU_SECTION_SIZE
+#define MMU_SECTION_SIZE (1 * 1024 * 1024)
+#endif
+
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
phys_size_t size;
diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig
new file mode 100644
index 000000000000..4bc9f72c541b
--- /dev/null
+++ b/board/xilinx/mbv/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_XILINX_MBV
+
+config SYS_BOARD
+ default "mbv"
+
+config SYS_VENDOR
+ default "xilinx"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "xilinx_mbv"
+
+config TEXT_BASE
+ default 0x80000000 if !RISCV_SMODE
+ default 0x80400000 if RISCV_SMODE && ARCH_RV32I
+
