If the system is in a dual parallel configuration, it's necessary to
halve the erase size since the erase command operates on two flashes
simultaneously. When dealing with a dual-stacked configuration,
determine whether the erase offset refers to the top or bottom flash,
and subsequently, adjust the flag for the relevant flash.
Consequently, the argument for the spi_nor_erase_sector function has
been modified from addr to offset.
Signed-off-by: Tejas Bhumkar <tejas.arvind.bhum...@amd.com>
---
drivers/mtd/spi/spi-nor-core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index d790116994..43435e79cc 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1078,7 +1078,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct
erase_info *instr)
if (nor->addr_width == 3) {
#ifdef CONFIG_SPI_FLASH_BAR
/* Update Extended Address Register */
- ret = write_bar(nor, addr);
+ ret = write_bar(nor, offset);
if (ret < 0)
goto erase_err;
#endif
@@ -1092,7 +1092,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct
erase_info *instr)
!(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
ret = spi_nor_erase_chip(nor);
} else {
- ret = spi_nor_erase_sector(nor, addr);
+ ret = spi_nor_erase_sector(nor, offset);
}
if (ret < 0)
goto erase_err;
--
2.27.0
