On 12/6/23 06:29, Tejas Bhumkar wrote:
A set of patches has been developed to resolve concerns regarding
data integrity failures in QSPI and OSPI for the Versal, Versal NET,
Zynq, and ZynqMP platforms.
The series has undergone testing with flashes on the default setup,
and comprehensive testing is currently underway to test the series
with all available flash parts.
These patches are built upon the v5 series, which can be found at
the following link:
https://lore.kernel.org/all/20231201031839.239567-1-venkatesh.abbar...@amd.com/
Algapally Santosh Sagar (1):
mtd: spi-nor-ids: Add support for W25Q02NW
Ashok Reddy Soma (10):
mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes
mtd: spi-nor: Add support for cross die read in dual flash
configuration
mtd: spi-nor: Enable DTR octal flash program
mtd: spi-nor: Send write disable cmd after every write enable
mtd: spi-nor: Check SNOR_F_IO_MODE_EN_VOLATILE only if SFDP is enabled
spi: cadence_qspi: Set tshsl_ns to at least one sclk_ns
spi: cadence_qspi: Clean up registers in init
spi: cadence_qspi: Initialize read and write watermark registers
spi: cadence_qspi: Enable ECO bit for higher frequencies
spi: cadence_qspi: Write aligned byte length to ahbbase
T Karthik Reddy (9):
mtd: spi-nor: Add config to enable flash DTR
mtd: spi-nor-core: Set dummy buswidth equal to data buswidth
spi: mtd: Use split reads if multi-die flag is set
mtd: spi-nor: program quad enable bit for winbond flashes
spi: cadence_qspi: Setup ddr mode in cadence qspi driver
spi: cadence-qspi: Switch SDR/DTR using SPI_FLASH_DTR_ENABLE config
spi: cadence_ospi_versal: ospi ddr changes in cadence ospi versal
driver
spi: cadence_qspi: Add spi mem dtr support ops
mtd: spi-nor: Add block protection support for micron flashes
Tejas Bhumkar (5):
arm64: versal: Enable defconfig for Micron octal flashes
mtd: spi-nor: Update erase operation function
spi: cadence_qspi: Fix versal ospi indirect write timed out issue
arm64: versal: Enable soft reset support for xspi flashes
arm64: versal: Enable octal DTR mode
Venkatesh Yadav Abbarapu (5):
mtd: spi-nor: Update block protection flags for flash parts
mtd: spi-nor: Add support for locking on Macronix nor flashes
mtd: spi-nor: Add support for locking on ISSI nor flashes
mtd: spi-nor: Add support for locking on GIGADEVICE nor flashes
mtd: spi-nor: Add support for locking on Spansion nor flashes
configs/xilinx_versal_virt_defconfig | 4 +
drivers/mtd/spi/Kconfig | 7 +
drivers/mtd/spi/sf_internal.h | 8 +
drivers/mtd/spi/spi-nor-core.c | 2028 +++++++++++++++++++++++---
drivers/mtd/spi/spi-nor-ids.c | 40 +-
drivers/spi/cadence_ospi_versal.c | 77 +-
drivers/spi/cadence_qspi.c | 403 ++++-
drivers/spi/cadence_qspi.h | 71 +
drivers/spi/cadence_qspi_apb.c | 107 +-
include/linux/mtd/spi-nor.h | 22 +
include/spi.h | 4 +-
11 files changed, 2545 insertions(+), 226 deletions(-)
Series it not send as one thread which confuse b4 and not able to get it from
lore. Can you please resend it with RESEND tag but with --thread enabled?
Thanks,
Michal
b4 am -l 20231206053353.3745918-1-tejas.arvind.bhum...@amd.com
Grabbing thread from
lore.kernel.org/all/20231206053353.3745918-1-tejas.arvind.bhumkar%40amd.com/t.mbox.gz
Analyzing 10 messages in the thread
Checking attestation on all messages, may take a moment...
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✓ [PATCH 10/30] mtd: spi-nor: program quad enable bit for winbond flashes
✓ Signed: DKIM/amd.com
+ Link:
https://lore.kernel.org/r/20231206053353.3745918-1-tejas.arvind.bhum...@amd.com
✓ [PATCH 11/30] mtd: spi-nor: Send write disable cmd after every write enable
✓ Signed: DKIM/amd.com
+ Link:
https://lore.kernel.org/r/20231206053353.3745918-2-tejas.arvind.bhum...@amd.com
✓ [PATCH 12/30] mtd: spi-nor: Update erase operation function
✓ Signed: DKIM/amd.com
+ Link:
https://lore.kernel.org/r/20231206053353.3745918-3-tejas.arvind.bhum...@amd.com
✓ [PATCH 13/30] mtd: spi-nor: Check SNOR_F_IO_MODE_EN_VOLATILE only if SFDP
is enabled
✓ Signed: DKIM/amd.com
+ Link:
https://lore.kernel.org/r/20231206053353.3745918-4-tejas.arvind.bhum...@amd.com
✓ [PATCH 14/30] spi: cadence_qspi: Setup ddr mode in cadence qspi driver
✓ Signed: DKIM/amd.com
+ Link:
https://lore.kernel.org/r/20231206053353.3745918-5-tejas.arvind.bhum...@amd.com
✓ [PATCH 15/30] spi: cadence-qspi: Switch SDR/DTR using SPI_FLASH_DTR_ENABLE
config
✓ Signed: DKIM/amd.com
+ Link:
https://lore.kernel.org/r/20231206053353.3745918-6-tejas.arvind.bhum...@amd.com
✓ [PATCH 16/30] spi: cadence_ospi_versal: ospi ddr changes in cadence ospi
versal driver
✓ Signed: DKIM/amd.com
+ Link:
https://lore.kernel.org/r/20231206053353.3745918-7-tejas.arvind.bhum...@amd.com
✓ [PATCH 17/30] spi: cadence_qspi: Fix versal ospi indirect write timed out
issue
✓ Signed: DKIM/amd.com
+ Link:
https://lore.kernel.org/r/20231206053353.3745918-8-tejas.arvind.bhum...@amd.com
✓ [PATCH 18/30] spi: cadence_qspi: Set tshsl_ns to at least one sclk_ns
✓ Signed: DKIM/amd.com
+ Link:
https://lore.kernel.org/r/20231206053353.3745918-9-tejas.arvind.bhum...@amd.com
✓ [PATCH 19/30] spi: cadence_qspi: Clean up registers in init
✓ Signed: DKIM/amd.com
+ Link:
https://lore.kernel.org/r/20231206053353.3745918-10-tejas.arvind.bhum...@amd.com
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