On 12/7/2023 2:47 AM, Reid Tonking wrote:
Previously, dynamic frequency scaling supported rates only through fixed
divison.

This virtual clock mux configuration enables more varied rates on A72
clock ID 202 by setting up the required register.

Signed-off-by: Apurva Nandan <a-nan...@ti.com>
Signed-off-by: Reid Tonking <re...@ti.com>
---
  arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts 
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index f0a73605020..018faaa13b6 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -24,7 +24,8 @@
                                <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
                resets = <&k3_reset 202 0>;
                clocks = <&k3_clks 61 1>;
-               assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
+               assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 
0>;
+               assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>;

For this patch

Reviewed-by: Udit Kumar <u-kum...@ti.com>


                assigned-clock-rates = <2000000000>, <200000000>;
                ti,sci = <&dmsc>;
                ti,sci-proc-id = <32>;

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