[PATCH 2/5] andes: ae350: Implement cache switch via Kconfig

[Leo Yu-Chi Liang]

Kconfig provides SYS_[I|D]CACHE_OFF config options
to switch off caches. Implement the corresponding options.

Signed-off-by: Leo Yu-Chi Liang <ycli...@andestech.com>
---
 arch/riscv/cpu/andesv5/cpu.c  | 9 +++++++--
 board/AndesTech/ae350/ae350.c | 3 ++-
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index 63bc24cdfc..50cd31905d 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -32,8 +32,13 @@ void harts_early_init(void)
        if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
                unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
 
-               mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
-                                  MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN);
+               mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_CCTL_SUEN | 
\
+
+       if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
+               mcache_ctl |= MCACHE_CTL_IC_EN;
+
+       if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
+               mcache_ctl |= MCACHE_CTL_DC_EN;
 
                csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
 
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index 772c6bf1ee..bef9e3149e 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -102,7 +102,8 @@ void *board_fdt_blob_setup(int *err)
 void spl_board_init()
 {
        /* enable v5l2 cache */
-       enable_caches();
+       if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+               enable_caches();
 }
 #endif
 
-- 
2.34.1