In clock_sun4i.c, responsible for (mostly early) clock setup on early
generation Allwinner SoCs, many functions are only needed by the SPL,
and are thus already guarded by CONFIG_SPL_BUILD.
Over the years drivers like for the UART or I2C were converted to DM,
so they care about clock setup themselves now, by using a proper DM clock
driver.
This means those devices need the clock setup functions here for the SPL
only. Include those functions into the existing CONFIG_SPL_BUILD guards,
so they are compiled for the SPL only.
This avoids unnecessary code in U-Boot proper and helps further
refactoring. Add some comments on the way to help understanding of the
file.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm/mach-sunxi/clock_sun4i.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-sunxi/clock_sun4i.c
b/arch/arm/mach-sunxi/clock_sun4i.c
index 8f1d1b65f00..eead5a924f4 100644
--- a/arch/arm/mach-sunxi/clock_sun4i.c
+++ b/arch/arm/mach-sunxi/clock_sun4i.c
@@ -41,7 +41,6 @@ void clock_init_safe(void)
setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
#endif
}
-#endif
void clock_init_uart(void)
{
@@ -75,7 +74,6 @@ int clock_twi_onoff(int port, int state)
return 0;
}
-#ifdef CONFIG_SPL_BUILD
#define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \
8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
@@ -175,8 +173,9 @@ void clock_set_pll1(unsigned int hz)
&ccm->cpu_ahb_apb0_cfg);
sdelay(20);
}
-#endif
+#endif /* CONFIG_SPL_BUILD */
+/* video, DRAM, PLL_PERIPH clocks */
void clock_set_pll3(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
--
2.35.8
