Hi Kever, On Tue, Jan 2, 2024 at 9:00 AM Kever Yang <kever.y...@rock-chips.com> wrote: > > Hi Tianling, > > On 2023/12/23 12:00, Tianling Shen wrote: > > The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board > > eMMC flash (8G) included. > > > > The device tree is taken from the kernel v6.5. > > > > Signed-off-by: Tianling Shen <cns...@gmail.com> > > --- > > arch/arm/dts/Makefile | 1 + > > .../dts/rk3328-nanopi-r2c-plus-u-boot.dtsi | 9 ++ > > arch/arm/dts/rk3328-nanopi-r2c-plus.dts | 33 +++++ > > board/rockchip/evb_rk3328/MAINTAINERS | 6 + > > configs/nanopi-r2c-plus-rk3328_defconfig | 114 ++++++++++++++++++ > > 5 files changed, 163 insertions(+) > > create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi > > create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus.dts > > create mode 100644 configs/nanopi-r2c-plus-rk3328_defconfig > > > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > > index 9d28a485bec..6909f95e084 100644 > > --- a/arch/arm/dts/Makefile > > +++ b/arch/arm/dts/Makefile > > @@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ > > dtb-$(CONFIG_ROCKCHIP_RK3328) += \ > > rk3328-evb.dtb \ > > rk3328-nanopi-r2c.dtb \ > > + rk3328-nanopi-r2c-plus.dtb \ > > rk3328-nanopi-r2s.dtb \ > > rk3328-orangepi-r1-plus.dtb \ > > rk3328-orangepi-r1-plus-lts.dtb \ > > diff --git a/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi > > b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi > > new file mode 100644 > > index 00000000000..f8adb9e5e1f > > --- /dev/null > > +++ b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi > > @@ -0,0 +1,9 @@ > > +// SPDX-License-Identifier: GPL-2.0-or-later > > + > > +#include "rk3328-nanopi-r2c-u-boot.dtsi" > > + > > +/ { > > + chosen { > > + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; > > + }; > > +}; > > diff --git a/arch/arm/dts/rk3328-nanopi-r2c-plus.dts > > b/arch/arm/dts/rk3328-nanopi-r2c-plus.dts > > new file mode 100644 > > index 00000000000..16a1958e457 > > --- /dev/null > > +++ b/arch/arm/dts/rk3328-nanopi-r2c-plus.dts > > @@ -0,0 +1,33 @@ > > +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT > > +/* > > + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. > > + * (http://www.friendlyarm.com) > > + * > > + * Copyright (c) 2023 Tianling Shen <cns...@gmail.com> > > + */ > > + > > +/dts-v1/; > > +#include "rk3328-nanopi-r2c.dts" > > + > > +/ { > > + model = "FriendlyElec NanoPi R2C Plus"; > > + compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328"; > > + > > + aliases { > > + mmc1 = &emmc; > > + }; > > +}; > > + > > +&emmc { > > + bus-width = <8>; > > + cap-mmc-highspeed; > > + max-frequency = <150000000>; > > + mmc-ddr-1_8v; > > + mmc-hs200-1_8v; > > + non-removable; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; > > + vmmc-supply = <&vcc_io_33>; > > + vqmmc-supply = <&vcc18_emmc>; > > + status = "okay"; > > +}; > > diff --git a/board/rockchip/evb_rk3328/MAINTAINERS > > b/board/rockchip/evb_rk3328/MAINTAINERS > > index 8a19eb373d0..5fc114a63f6 100644 > > --- a/board/rockchip/evb_rk3328/MAINTAINERS > > +++ b/board/rockchip/evb_rk3328/MAINTAINERS > > @@ -11,6 +11,12 @@ S: Maintained > > F: configs/nanopi-r2c-rk3328_defconfig > > F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi > > > > +NANOPI-R2C-PLUS-RK3328 > > +M: Tianling Shen <cns...@gmail.com> > > +S: Maintained > > +F: configs/nanopi-r2c-plus-rk3328_defconfig > > +F: arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi > > + > > NANOPI-R2S-RK3328 > > M: David Bauer <m...@david-bauer.net> > > S: Maintained > > diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig > > b/configs/nanopi-r2c-plus-rk3328_defconfig > > new file mode 100644 > > index 00000000000..320ed8b434a > > --- /dev/null > > +++ b/configs/nanopi-r2c-plus-rk3328_defconfig > > @@ -0,0 +1,114 @@ > > +CONFIG_ARM=y > > +CONFIG_SKIP_LOWLEVEL_INIT=y > > +CONFIG_COUNTER_FREQUENCY=24000000 > > +CONFIG_ARCH_ROCKCHIP=y > > +CONFIG_TEXT_BASE=0x00200000 > > +CONFIG_SPL_GPIO=y > > +CONFIG_NR_DRAM_BANKS=1 > > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y > > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 > > +CONFIG_SF_DEFAULT_SPEED=20000000 > > +CONFIG_ENV_OFFSET=0x3F8000 > > +CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus" > > +CONFIG_DM_RESET=y > > +CONFIG_ROCKCHIP_RK3328=y > > +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y > > +CONFIG_TPL_LIBCOMMON_SUPPORT=y > > +CONFIG_TPL_LIBGENERIC_SUPPORT=y > > +CONFIG_SPL_DRIVERS_MISC=y > > +CONFIG_SPL_STACK_R_ADDR=0x600000 > > +CONFIG_SPL_STACK=0x400000 > > +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 > > Did you test both TPL and SPL?
Yes, I have confirmed both TPL and SPL are working fine. Thanks, Tianling. > > > Thanks, > > - Kever > > > +CONFIG_DEBUG_UART_BASE=0xFF130000 > > +CONFIG_DEBUG_UART_CLOCK=24000000 > > +CONFIG_SYS_LOAD_ADDR=0x800800 > > +CONFIG_DEBUG_UART=y > > +# CONFIG_ANDROID_BOOT_IMAGE is not set > > +CONFIG_FIT=y > > +CONFIG_FIT_VERBOSE=y > > +CONFIG_SPL_LOAD_FIT=y > > +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb" > > +# CONFIG_DISPLAY_CPUINFO is not set > > +CONFIG_DISPLAY_BOARDINFO_LATE=y > > +CONFIG_MISC_INIT_R=y > > +CONFIG_SPL_MAX_SIZE=0x40000 > > +CONFIG_SPL_PAD_TO=0x7f8000 > > +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y > > +CONFIG_SPL_BSS_START_ADDR=0x2000000 > > +CONFIG_SPL_BSS_MAX_SIZE=0x2000 > > +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > > +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set > > +CONFIG_SPL_STACK_R=y > > +CONFIG_SPL_I2C=y > > +CONFIG_SPL_POWER=y > > +CONFIG_SPL_ATF=y > > +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y > > +CONFIG_TPL_SYS_MALLOC_SIMPLE=y > > +CONFIG_CMD_BOOTZ=y > > +CONFIG_CMD_GPT=y > > +CONFIG_CMD_MMC=y > > +CONFIG_CMD_USB=y > > +# CONFIG_CMD_SETEXPR is not set > > +CONFIG_CMD_TIME=y > > +CONFIG_SPL_OF_CONTROL=y > > +CONFIG_TPL_OF_CONTROL=y > > +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks > > assigned-clock-rates assigned-clock-parents" > > +CONFIG_TPL_OF_PLATDATA=y > > +CONFIG_ENV_IS_IN_MMC=y > > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y > > +CONFIG_SYS_MMC_ENV_DEV=1 > > +CONFIG_NET_RANDOM_ETHADDR=y > > +CONFIG_TPL_DM=y > > +CONFIG_REGMAP=y > > +CONFIG_SPL_REGMAP=y > > +CONFIG_TPL_REGMAP=y > > +CONFIG_SYSCON=y > > +CONFIG_SPL_SYSCON=y > > +CONFIG_TPL_SYSCON=y > > +CONFIG_CLK=y > > +CONFIG_SPL_CLK=y > > +CONFIG_FASTBOOT_BUF_ADDR=0x800800 > > +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y > > +CONFIG_ROCKCHIP_GPIO=y > > +CONFIG_SYS_I2C_ROCKCHIP=y > > +CONFIG_MISC=y > > +CONFIG_MMC_DW=y > > +CONFIG_MMC_DW_ROCKCHIP=y > > +CONFIG_ETH_DESIGNWARE=y > > +CONFIG_GMAC_ROCKCHIP=y > > +CONFIG_PHY_ROCKCHIP_INNO_USB2=y > > +CONFIG_PINCTRL=y > > +CONFIG_SPL_PINCTRL=y > > +CONFIG_DM_PMIC=y > > +CONFIG_PMIC_RK8XX=y > > +CONFIG_SPL_PMIC_RK8XX=y > > +CONFIG_SPL_DM_REGULATOR=y > > +CONFIG_REGULATOR_PWM=y > > +CONFIG_DM_REGULATOR_FIXED=y > > +CONFIG_SPL_DM_REGULATOR_FIXED=y > > +CONFIG_REGULATOR_RK8XX=y > > +CONFIG_PWM_ROCKCHIP=y > > +CONFIG_RAM=y > > +CONFIG_SPL_RAM=y > > +CONFIG_TPL_RAM=y > > +CONFIG_BAUDRATE=1500000 > > +CONFIG_DEBUG_UART_SHIFT=2 > > +CONFIG_SYS_NS16550_MEM32=y > > +CONFIG_SYSINFO=y > > +CONFIG_SYSRESET=y > > +# CONFIG_TPL_SYSRESET is not set > > +CONFIG_USB=y > > +CONFIG_USB_XHCI_HCD=y > > +CONFIG_USB_EHCI_HCD=y > > +CONFIG_USB_EHCI_GENERIC=y > > +CONFIG_USB_OHCI_HCD=y > > +CONFIG_USB_OHCI_GENERIC=y > > +CONFIG_USB_DWC2=y > > +CONFIG_USB_DWC3=y > > +# CONFIG_USB_DWC3_GADGET is not set > > +CONFIG_USB_DWC3_GENERIC=y > > +CONFIG_USB_GADGET=y > > +CONFIG_USB_GADGET_DWC2_OTG=y > > +CONFIG_SPL_TINY_MEMSET=y > > +CONFIG_TPL_TINY_MEMSET=y > > +CONFIG_ERRNO_STR=y