Hi Tom, Please pull the SoCFPGA changes as shown in below.
Best regards, Tien Fong The following changes since commit 3c04fcf3137d5f694d52b8f355373e4baabe5f78: Merge patch series "k3-j721e: beagleboneai: Fix USB" (2024-01-20 11:39:13 -0500) are available in the Git repository at: https://github.com/tienfong/uboot_mainline.git 3c9bb8fbdc77f6bd56e97597d875d8965db3b96c for you to fetch changes up to 3c9bb8fbdc77f6bd56e97597d875d8965db3b96c: arm: dts: agilex: Increase reserved memory size to 32MB (2024-01-22 16:51:29 +0800) ---------------------------------------------------------------- Dinesh Maniyam (3): arm: socfpga: stratix10: SPI clock support clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0) arm: dts: agilex: Increase reserved memory size to 32MB arch/arm/dts/socfpga_agilex.dtsi | 4 ++-- arch/arm/mach-socfpga/clock_manager_s10.c | 17 ++++++++++++++++- drivers/clk/altera/clk-mem-n5x.h | 4 ++-- 3 files changed, 20 insertions(+), 5 deletions(-)