[PATCH 1/1] sunxi: sun4i: Reduce cpu clock at SPL initialization to 144 MHz

[Ludwig Kormann]

Up until now cpu clock gets initialized at 384 MHz, which is
the highest supported cpu clock.

Recent A20 batches show an increased percentage of modules
reacting very sensitive to operating conditions outside the
specifications.

The cpu dies very shortly after PLLs, core frequency or cpu
voltage are missconfigured. E.g.:
- uboot SPL selects 384 MHz as cpu clock which requires a cpu
  voltage of at least 1.1 V.
- Linux CPU Frequency scaling with most sun7i dts will reduce
  cpu voltage down to 1.0 V.
- When intiating a reboot or reset from linux the cpu voltage
  may keep the 1.0 V configuration and the cpu dies during SPL
  initialization.

Therefore reduce cpu clock at uboot SPL initialization down
to 144 MHz from 384 MHz.

Signed-off-by: Ludwig Kormann <ludwig.korm...@ict42.de>
---
 arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 2 +-
 arch/arm/mach-sunxi/clock_sun4i.c             | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 2cec91cb20..252c4c693e 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -141,7 +141,7 @@ struct sunxi_ccm_reg {
 #define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT     2
 #define CCM_PLL1_CFG_FACTOR_M_SHIFT            0
 
-#define PLL1_CFG_DEFAULT       0xa1005000
+#define PLL1_CFG_DEFAULT       0xa1004c01
 
 #if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I
 /*
diff --git a/arch/arm/mach-sunxi/clock_sun4i.c 
b/arch/arm/mach-sunxi/clock_sun4i.c
index 8f1d1b65f0..ac3b7a801f 100644
--- a/arch/arm/mach-sunxi/clock_sun4i.c
+++ b/arch/arm/mach-sunxi/clock_sun4i.c
@@ -25,6 +25,7 @@ void clock_init_safe(void)
               APB0_DIV_1 << APB0_DIV_SHIFT |
               CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
               &ccm->cpu_ahb_apb0_cfg);
+       sdelay(20);
        writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
        sdelay(200);
        writel(AXI_DIV_1 << AXI_DIV_SHIFT |
@@ -32,6 +33,7 @@ void clock_init_safe(void)
               APB0_DIV_1 << APB0_DIV_SHIFT |
               CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
               &ccm->cpu_ahb_apb0_cfg);
+       sdelay(20);
 #ifdef CONFIG_MACH_SUN7I
        setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
 #endif
-- 
2.39.2