On 1/25/24 09:07, Michal Simek wrote:
From: Saeed Nowshadi <saeed.nowsh...@amd.com> Without 'silabs,skip-recall' property, the driver on System Controller re-calibrates the output clock frequency at probe() time based on the NVRAM setting. This re-calibration causes a glitch on the output clock. At power-on, Versal is also booting and expecting a glitch-free clock for its correct operation. System Controller should skip the re-calibration step to prevent any clock instability for Versal. Signed-off-by: Saeed Nowshadi <saeed.nowsh...@amd.com> Signed-off-by: Michal Simek <michal.si...@amd.com> --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index f1b0a4aa65dd..0b97fa3f28ac 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -449,6 +449,7 @@ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; + silabs,skip-recall; }; }; i2c@6 { /* USER_SI570_1 */ @@ -463,6 +464,7 @@ factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; + silabs,skip-recall; };};@@ -560,6 +562,7 @@ factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; + silabs,skip-recall; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ @@ -574,6 +577,7 @@ factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; + silabs,skip-recall; }; }; i2c@6 { /* HSDP_SI570 */ @@ -588,6 +592,7 @@ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; + silabs,skip-recall; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */
Applied. M
