Hi Jit loon, > -----Original Message----- > From: Lim, Jit Loon <jit.loon....@intel.com> > Sent: Thursday, March 7, 2024 12:42 AM > To: u-boot@lists.denx.de > Cc: Jagan Teki <ja...@amarulasolutions.com>; Marek <ma...@denx.de>; > Simon <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong > <tien.fong.c...@intel.com>; Hea, Kok Kiang <kok.kiang....@intel.com>; > Maniyam, Dinesh <dinesh.mani...@intel.com>; Ng, Boon Khai > <boon.khai...@intel.com>; Yuslaimi, Alif Zakuan > <alif.zakuan.yusla...@intel.com>; Chong, Teik Heng > <teik.heng.ch...@intel.com>; Zamri, Muhammad Hazim Izzat > <muhammad.hazim.izzat.za...@intel.com>; Lim, Jit Loon > <jit.loon....@intel.com>; Tang, Sieu Mun <sieu.mun.t...@intel.com>; Bin > Meng <bmeng...@gmail.com> > Subject: [RESEND v2 1/1] arch: arm: Agilex5 enablement > > This patch is to enable Agilex5 platform for Intel > product. Changes, modification and new files are > created for board, dts, configs and makefile to > create the base for Agilex5. > > Signed-off-by: Jit Loon Lim <jit.loon....@intel.com> > > --- > Changes v1 -> v2: > - fixed git auto merge issue > ---
[...] > --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c > +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0 > /* > - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> > + * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> > * > */ > > @@ -10,6 +10,62 @@ > > DECLARE_GLOBAL_DATA_PTR; > > +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) > +static struct mm_region socfpga_agilex5_mem_map[] = { > + { > + /* OCRAM 512KB */ > + .virt = 0x00000000UL, > + .phys = 0x00000000UL, > + .size = 0x00080000UL, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE, > + }, { > + /* DEVICE */ > + .virt = 0x10808000UL, > + .phys = 0x10808000UL, > + .size = 0x0F7F8000UL, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN, > + }, { > + /* FPGA 1.5GB */ > + .virt = 0x20000000UL, > + .phys = 0x20000000UL, > + .size = 0x60000000UL, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN, > + }, { > + /* FPGA 15GB */ > + .virt = 0x440000000UL, > + .phys = 0x440000000UL, > + .size = 0x3C0000000UL, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN, > + }, { > + /* FPGA 240GB */ > + .virt = 0x4400000000UL, > + .phys = 0x4400000000UL, > + .size = 0x3E80000000UL, This size is not 240GB, please correct it. [...] Best regards, Tien Fong