Hi Jit Loon, > -----Original Message----- > From: Lim, Jit Loon <jit.loon....@intel.com> > Sent: Monday, March 11, 2024 9:52 AM > To: u-boot@lists.denx.de > Cc: Jagan Teki <ja...@amarulasolutions.com>; Marek <ma...@denx.de>; > Simon <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong > <tien.fong.c...@intel.com>; Hea, Kok Kiang <kok.kiang....@intel.com>; > Maniyam, Dinesh <dinesh.mani...@intel.com>; Ng, Boon Khai > <boon.khai...@intel.com>; Yuslaimi, Alif Zakuan > <alif.zakuan.yusla...@intel.com>; Chong, Teik Heng > <teik.heng.ch...@intel.com>; Zamri, Muhammad Hazim Izzat > <muhammad.hazim.izzat.za...@intel.com>; Lim, Jit Loon > <jit.loon....@intel.com>; Tang, Sieu Mun <sieu.mun.t...@intel.com>; Bin > Meng <bmeng...@gmail.com> > Subject: [PATCH v3 v3 1/1] arch: arm: Agilex5 enablement > > This patch is to enable Agilex5 platform for Intel > product. Changes, modification and new files are > created for board, dts, configs and makefile to > create the base for Agilex5. > > Signed-off-by: Jit Loon Lim <jit.loon....@intel.com> > > Changes v2 -> v3: > - Added FPGA 240G DDR region > Changes v1 -> v2: > - fixed git auto merge issue > --- > arch/arm/Kconfig | 4 +- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 71 ++ > arch/arm/dts/socfpga_agilex5.dtsi | 575 ++++++++++++++ > .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 133 ++++ > arch/arm/dts/socfpga_agilex5_socdk.dts | 163 ++++ > arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 38 +- > arch/arm/mach-socfpga/Kconfig | 19 +- > arch/arm/mach-socfpga/Makefile | 14 +- > arch/arm/mach-socfpga/board.c | 56 +- > arch/arm/mach-socfpga/clock_manager_agilex5.c | 89 +++ > .../include/mach/base_addr_soc64.h | 38 +- > .../mach-socfpga/include/mach/clock_manager.h | 4 +- > .../include/mach/clock_manager_agilex5.h | 12 + > .../mach-socfpga/include/mach/handoff_soc64.h | 31 +- > .../mach-socfpga/include/mach/mailbox_s10.h | 1 + > arch/arm/mach-socfpga/mmu-arm64_s10.c | 59 +- > board/intel/agilex5-socdk/MAINTAINERS | 8 + > configs/socfpga_agilex5_defconfig | 116 +++ > drivers/clk/altera/Makefile | 1 + > drivers/clk/altera/clk-agilex5.c | 743 ++++++++++++++++++ > drivers/clk/altera/clk-agilex5.h | 284 +++++++ > include/configs/socfpga_agilex5_socdk.h | 12 + > include/configs/socfpga_soc64_common.h | 143 +++- > include/dt-bindings/clock/agilex5-clock.h | 71 ++ > include/dt-bindings/reset/altr,rst-mgr-agx5.h | 80 ++ > 26 files changed, 2730 insertions(+), 36 deletions(-) > create mode 100644 arch/arm/dts/socfpga_agilex5-u-boot.dtsi > create mode 100644 arch/arm/dts/socfpga_agilex5.dtsi > create mode 100644 arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi > create mode 100644 arch/arm/dts/socfpga_agilex5_socdk.dts > create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex5.c > create mode 100644 arch/arm/mach- > socfpga/include/mach/clock_manager_agilex5.h > create mode 100644 board/intel/agilex5-socdk/MAINTAINERS > create mode 100644 configs/socfpga_agilex5_defconfig > create mode 100644 drivers/clk/altera/clk-agilex5.c > create mode 100644 drivers/clk/altera/clk-agilex5.h > create mode 100644 include/configs/socfpga_agilex5_socdk.h > create mode 100644 include/dt-bindings/clock/agilex5-clock.h > create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agx5.h >
[...] > diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi > b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi > new file mode 100644 > index 0000000000..a24b0482bb > --- /dev/null > +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi > @@ -0,0 +1,133 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * U-Boot additions > + * > + * Copyright (C) 2024 Intel Corporation <www.intel.com> > + */ > + > +#include "socfpga_agilex5-u-boot.dtsi" > + > +/{ > + aliases { > + spi0 = &qspi; > + freeze_br0 = &freeze_controller; > + }; [...] > + > +#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH) Using IS_enabled() > +&fdt_0_blob { > + filename = "arch/arm/dts/socfpga_agilex5_socdk.dtb"; > +}; [...] Best regards Tien Fong