[PATCH v2 2/5] apq8016: Add support for UART1 clocks and pinmux

[Sumit Garg]

SE HMIBSC board uses UART1 as the main debug console, so add
corresponding clocks and pinmux support. Along with that update
instructions to enable clocks for debug UART support.

Signed-off-by: Sumit Garg <sumit.g...@linaro.org>
---
 drivers/clk/qcom/clock-apq8016.c       | 50 +++++++++++++++++++++-----
 drivers/pinctrl/qcom/pinctrl-apq8016.c |  1 +
 drivers/serial/serial_msm.c            |  6 ++--
 3 files changed, 47 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index e6647f7c41d..a620a10a520 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -43,6 +43,14 @@
 #define BLSP1_UART2_APPS_N             (0x3040)
 #define BLSP1_UART2_APPS_D             (0x3044)
 
+#define BLSP1_UART1_BCR                        (0x2038)
+#define BLSP1_UART1_APPS_CBCR          (0x203C)
+#define BLSP1_UART1_APPS_CMD_RCGR      (0x2044)
+#define BLSP1_UART1_APPS_CFG_RCGR      (0x2048)
+#define BLSP1_UART1_APPS_M             (0x204C)
+#define BLSP1_UART1_APPS_N             (0x2050)
+#define BLSP1_UART1_APPS_D             (0x2054)
+
 /* GPLL0 clock control registers */
 #define GPLL0_STATUS_ACTIVE BIT(17)
 
@@ -77,7 +85,7 @@ static struct vote_clk gcc_blsp1_ahb_clk = {
 };
 
 /* SDHCI */
-static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
+static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
 {
        int div = 15; /* 100MHz default */
 
@@ -94,6 +102,33 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int 
slot, uint rate)
        return rate;
 }
 
+static const struct bcr_regs uart1_regs = {
+       .cfg_rcgr = BLSP1_UART1_APPS_CFG_RCGR,
+       .cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR,
+       .M = BLSP1_UART1_APPS_M,
+       .N = BLSP1_UART1_APPS_N,
+       .D = BLSP1_UART1_APPS_D,
+};
+
+/* UART: 115200 */
+static int apq8016_clk_init_uart1(phys_addr_t base)
+{
+       /* Enable AHB clock */
+       clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk);
+
+       /* 7372800 uart block clock @ GPLL0 */
+       clk_rcg_set_rate_mnd(base, &uart1_regs, 1, 144, 15625,
+                            CFG_CLK_SRC_GPLL0, 16);
+
+       /* Vote for gpll0 clock */
+       clk_enable_gpll0(base, &gpll0_vote_clk);
+
+       /* Enable core clk */
+       clk_enable_cbc(base + BLSP1_UART1_APPS_CBCR);
+
+       return 0;
+}
+
 static const struct bcr_regs uart2_regs = {
        .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
        .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
@@ -103,7 +138,7 @@ static const struct bcr_regs uart2_regs = {
 };
 
 /* UART: 115200 */
-int apq8016_clk_init_uart(phys_addr_t base)
+int apq8016_clk_init_uart2(phys_addr_t base)
 {
        /* Enable AHB clock */
        clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk);
@@ -127,14 +162,13 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong 
rate)
 
        switch (clk->id) {
        case GCC_SDCC1_APPS_CLK: /* SDC1 */
-               return clk_init_sdc(priv, 0, rate);
-               break;
+               return apq8016_clk_init_sdc(priv, 0, rate);
        case GCC_SDCC2_APPS_CLK: /* SDC2 */
-               return clk_init_sdc(priv, 1, rate);
-               break;
+               return apq8016_clk_init_sdc(priv, 1, rate);
        case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
-               return apq8016_clk_init_uart(priv->base);
-               break;
+               return apq8016_clk_init_uart2(priv->base);
+       case GCC_BLSP1_UART1_APPS_CLK: /* UART1 */
+               return apq8016_clk_init_uart1(priv->base);
        default:
                return 0;
        }
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c 
b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index db0e2124684..cb0e2227079 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = {
 };
 
 static const struct pinctrl_function msm_pinctrl_functions[] = {
+       {"blsp_uart1", 2},
        {"blsp_uart2", 2},
 };
 
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index ac4280c6c4c..eaf024a55b0 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -248,12 +248,14 @@ static struct msm_serial_data init_serial_data = {
 #include <debug_uart.h>
 
 /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 
*/
-//int apq8016_clk_init_uart(phys_addr_t gcc_base);
+//int apq8016_clk_init_uart1(phys_addr_t gcc_base);
+//int apq8016_clk_init_uart2(phys_addr_t gcc_base);
 
 static inline void _debug_uart_init(void)
 {
        /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on 
MSM8916 */
-       //apq8016_clk_init_uart(0x1800000);
+       //apq8016_clk_init_uart1(0x1800000);
+       //apq8016_clk_init_uart2(0x1800000);
        uart_dm_init(&init_serial_data);
 }
 
-- 
2.34.1