On Tue, Mar 05, 2024 at 07:00:11PM -0800, Bo Gan wrote: > Previously PLL node was missing from SPL dts. This caused BUS_ROOT > to stay on OSC clock (24Mhz). As a result, all peripherals have to > run at a much lower frequency, and loading from sdcard/emmc is slow. > Thus, enabling PLL node in dts to fix this. > > Signed-off-by: Bo Gan <ganbo...@gmail.com> > --- > arch/riscv/dts/jh7110-u-boot.dtsi | 4 ++++ > 1 file changed, 4 insertions(+)
Reviewed-by: Leo Yu-Chi Liang <ycli...@andestech.com>
