On Tue, 12 Mar 2024 at 03:03, Volodymyr Babchuk <volodymyr_babc...@epam.com> wrote: > > The current behaviour does a bitwise OR of the previous and new > divider values, this is wrong as some bits maybe be set already. We
nit: s/maybe be/maybe/ > need to clear all the divider bits before applying new ones. > > This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards. > > Signed-off-by: Volodymyr Babchuk <volodymyr_babc...@epam.com> > Reviewed-by: Caleb Connolly <caleb.conno...@linaro.org> > Reviewed-by: Sumit Garg <sumit.g...@linaro.org> -Sumit > --- > > (no changes since v2) > > Changes in v2: > - Reworded the commit message > - Added Caleb's R-b tag > > drivers/clk/qcom/clock-qcom.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c > index 7c683e5192..729d190c54 100644 > --- a/drivers/clk/qcom/clock-qcom.c > +++ b/drivers/clk/qcom/clock-qcom.c > @@ -117,7 +117,8 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct > bcr_regs *regs, > > /* setup src select and divider */ > cfg = readl(base + regs->cfg_rcgr); > - cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK); > + cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK | > + CFG_SRC_DIV_MASK); > cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */ > > if (div) > -- > 2.43.0
