Adding support for pcf2131 RTC chip.
The pcf2131 is similar to the pcf2127. The driver support rtc register
read/write by using rtc cmd and rtc date set/get by using date cmd.
The pcf2131 is special when write access to time registers. it requires
setting the STOP and CPR bits. STOP bit needs to be cleared after time
registers are updated.
Signed-off-by: Joy Zou <joy....@nxp.com>
---
Changes in v3:
1.merge pcf2131 into pcf2127 in order to keep same with kernel.
Changes in v2:
1. delete the unnecessary initialization.
2. retrun directly function insteand of redundancy return ret.
3. delete the unnecessary comment line.
---
drivers/rtc/pcf2127.c | 144 ++++++++++++++++++++++++++++++++++++++----
1 file changed, 131 insertions(+), 13 deletions(-)
diff --git a/drivers/rtc/pcf2127.c b/drivers/rtc/pcf2127.c
index 2f3fafb496..58ab5a8601 100644
--- a/drivers/rtc/pcf2127.c
+++ b/drivers/rtc/pcf2127.c
@@ -23,6 +23,38 @@
#define PCF2127_REG_MO 0x08
#define PCF2127_REG_YR 0x09
+#define PCF2131_REG_CTRL1 0x00
+#define PCF2131_BIT_CTRL1_STOP BIT(5)
+#define PCF2131_REG_SR_RESET 0x05
+#define PCF2131_SR_VAL_Clr_Pres 0xa4
+#define PCF2131_REG_SC 0x07
+#define PCF2131_REG_MN 0x08
+#define PCF2131_REG_HR 0x09
+#define PCF2131_REG_DM 0x0a
+#define PCF2131_REG_DW 0x0b
+#define PCF2131_REG_MO 0x0c
+#define PCF2131_REG_YR 0x0d
+
+enum {
+ NXP_CHIP_TYPE_PCF2127 = 0,
+ NXP_CHIP_TYPE_PCF2129,
+ NXP_CHIP_TYPE_PCA2129,
+ NXP_CHIP_TYPE_PCF2131,
+ NXP_CHIP_TYPE_AMOUNT
+};
+
+bool is_pcf2131_type(struct udevice *dev)
+{
+ int type;
+
+ type = dev_get_driver_data(dev);
+
+ if (type == NXP_CHIP_TYPE_PCF2131)
+ return true;
+ else
+ return false;
+}
+
static int pcf2127_rtc_read(struct udevice *dev, uint offset, u8 *buffer, uint
len)
{
struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
@@ -43,10 +75,64 @@ static int pcf2127_rtc_read(struct udevice *dev, uint
offset, u8 *buffer, uint l
return dm_i2c_xfer(dev, &msg, 1);
}
+static int pcf2131_rtc_lock(struct udevice *dev)
+{
+ int ret = 0;
+ uchar buf[6] = { PCF2131_REG_CTRL1 };
+
+ ret = pcf2127_rtc_read(dev, PCF2131_REG_CTRL1, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ buf[PCF2131_REG_CTRL1] |= PCF2131_BIT_CTRL1_STOP;
+ ret = dm_i2c_write(dev, PCF2131_REG_CTRL1, &buf[PCF2131_REG_CTRL1], 1);
+ if (ret < 0)
+ return ret;
+
+ buf[PCF2131_REG_SR_RESET] = PCF2131_SR_VAL_Clr_Pres;
+
+ return dm_i2c_write(dev, PCF2131_REG_SR_RESET,
&buf[PCF2131_REG_SR_RESET], 1);
+}
+
+static int pcf2131_rtc_unlock(struct udevice *dev)
+{
+ int ret = 0;
+ uchar buf[6] = { PCF2131_REG_CTRL1 };
+
+ ret = pcf2127_rtc_read(dev, PCF2131_REG_CTRL1, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ buf[PCF2131_REG_CTRL1] &= ~PCF2131_BIT_CTRL1_STOP;
+ return dm_i2c_write(dev, PCF2131_REG_CTRL1, &buf[PCF2131_REG_CTRL1], 1);
+}
+
static int pcf2127_rtc_write(struct udevice *dev, uint offset,
const u8 *buffer, uint len)
{
- return dm_i2c_write(dev, offset, buffer, len);
+ int ret = 0;
+ bool flag;
+
+ flag = is_pcf2131_type(dev);
+ if (flag) {
+ ret = pcf2131_rtc_lock(dev);
+ if (ret < 0)
+ return ret;
+ }
+
+ ret = dm_i2c_write(dev, offset, buffer, len);
+ if (ret < 0) {
+ if (flag)
+ pcf2131_rtc_unlock(dev);
+ return ret;
+ }
+
+ if (flag) {
+ ret = pcf2131_rtc_unlock(dev);
+ if (ret < 0)
+ return ret;
+ }
+ return ret;
}
static int pcf2127_rtc_set(struct udevice *dev, const struct rtc_time *tm)
@@ -68,7 +154,10 @@ static int pcf2127_rtc_set(struct udevice *dev, const
struct rtc_time *tm)
buf[i++] = bin2bcd(tm->tm_year % 100);
/* write register's data */
- ret = dm_i2c_write(dev, PCF2127_REG_SC, buf, i);
+ if (is_pcf2131_type(dev))
+ ret = pcf2127_rtc_write(dev, PCF2131_REG_SC, buf, i);
+ else
+ ret = pcf2127_rtc_write(dev, PCF2127_REG_SC, buf, i);
return ret;
}
@@ -76,7 +165,8 @@ static int pcf2127_rtc_set(struct udevice *dev, const struct
rtc_time *tm)
static int pcf2127_rtc_get(struct udevice *dev, struct rtc_time *tm)
{
int ret = 0;
- uchar buf[10] = { PCF2127_REG_CTRL1 };
+ bool flag;
+ uchar buf[14] = { PCF2127_REG_CTRL1 };
ret = pcf2127_rtc_read(dev, PCF2127_REG_CTRL1, buf, sizeof(buf));
if (ret < 0)
@@ -85,15 +175,28 @@ static int pcf2127_rtc_get(struct udevice *dev, struct
rtc_time *tm)
if (buf[PCF2127_REG_CTRL3] & 0x04)
puts("### Warning: RTC Low Voltage - date/time not reliable\n");
- tm->tm_sec = bcd2bin(buf[PCF2127_REG_SC] & 0x7F);
- tm->tm_min = bcd2bin(buf[PCF2127_REG_MN] & 0x7F);
- tm->tm_hour = bcd2bin(buf[PCF2127_REG_HR] & 0x3F);
- tm->tm_mday = bcd2bin(buf[PCF2127_REG_DM] & 0x3F);
- tm->tm_mon = bcd2bin(buf[PCF2127_REG_MO] & 0x1F);
- tm->tm_year = bcd2bin(buf[PCF2127_REG_YR]) + 1900;
+ flag = is_pcf2131_type(dev);
+ if (flag) {
+ tm->tm_sec = bcd2bin(buf[PCF2131_REG_SC] & 0x7F);
+ tm->tm_min = bcd2bin(buf[PCF2131_REG_MN] & 0x7F);
+ tm->tm_hour = bcd2bin(buf[PCF2131_REG_HR] & 0x3F);
+ tm->tm_mday = bcd2bin(buf[PCF2131_REG_DM] & 0x3F);
+ tm->tm_mon = bcd2bin(buf[PCF2131_REG_MO] & 0x1F);
+ tm->tm_year = bcd2bin(buf[PCF2131_REG_YR]) + 1900;
+ } else {
+ tm->tm_sec = bcd2bin(buf[PCF2127_REG_SC] & 0x7F);
+ tm->tm_min = bcd2bin(buf[PCF2127_REG_MN] & 0x7F);
+ tm->tm_hour = bcd2bin(buf[PCF2127_REG_HR] & 0x3F);
+ tm->tm_mday = bcd2bin(buf[PCF2127_REG_DM] & 0x3F);
+ tm->tm_mon = bcd2bin(buf[PCF2127_REG_MO] & 0x1F);
+ tm->tm_year = bcd2bin(buf[PCF2127_REG_YR]) + 1900;
+ }
if (tm->tm_year < 1970)
tm->tm_year += 100; /* assume we are in 1970...2069 */
- tm->tm_wday = buf[PCF2127_REG_DW] & 0x07;
+ if (flag)
+ tm->tm_wday = buf[PCF2131_REG_DW] & 0x07;
+ else
+ tm->tm_wday = buf[PCF2127_REG_DW] & 0x07;
tm->tm_yday = 0;
tm->tm_isdst = 0;
@@ -111,6 +214,19 @@ static int pcf2127_rtc_reset(struct udevice *dev)
return 0;
}
+static int pcf2127_probe(struct udevice *dev)
+{
+ struct udevice *bus, *udev;
+ struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
+
+ if (is_pcf2131_type(dev)) {
+ bus = dev_get_parent(dev);
+ return dm_i2c_probe(bus, chip->chip_addr, 0, &udev);
+ }
+
+ return 0;
+}
+
static const struct rtc_ops pcf2127_rtc_ops = {
.get = pcf2127_rtc_get,
.set = pcf2127_rtc_set,
@@ -120,9 +236,10 @@ static const struct rtc_ops pcf2127_rtc_ops = {
};
static const struct udevice_id pcf2127_rtc_ids[] = {
- { .compatible = "nxp,pcf2127" },
- { .compatible = "nxp,pcf2129" },
- { .compatible = "nxp,pca2129" },
+ { .compatible = "nxp,pcf2127", .data = NXP_CHIP_TYPE_PCF2127, },
+ { .compatible = "nxp,pcf2129", .data = NXP_CHIP_TYPE_PCF2129, },
+ { .compatible = "nxp,pca2129", .data = NXP_CHIP_TYPE_PCA2129, },
+ { .compatible = "nxp,pcf2131", .data = NXP_CHIP_TYPE_PCF2131, },
{ }
};
@@ -131,4 +248,5 @@ U_BOOT_DRIVER(rtc_pcf2127) = {
.id = UCLASS_RTC,
.of_match = pcf2127_rtc_ids,
.ops = &pcf2127_rtc_ops,
+ .probe = pcf2127_probe,
};
--
2.37.1
