[PATCH 08/11] spi: cadence-quadspi: Direct mode does not support zero length addresses

[Greg Malysa]

From: Ian Roberts <ian.robe...@timesys.com>

It is not possible to configure the Cadence SPI IP block to use a zero
length address in DMA read or write commands.

Co-developed-by: Nathan Barrett-Morrison <nathan.morri...@timesys.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morri...@timesys.com>
Signed-off-by: Greg Malysa <greg.mal...@timesys.com>
Signed-off-by: Ian Roberts <ian.robe...@timesys.com>
---

 drivers/spi/cadence_qspi_apb.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 2600370f85..340889c271 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -784,7 +784,7 @@ int cadence_qspi_apb_read_execute(struct cadence_spi_priv 
*priv,
 
        cadence_qspi_apb_enable_linear_mode(true);
 
-       if (priv->use_dac_mode && (from + len < priv->ahbsize)) {
+       if (op->addr.nbytes && priv->use_dac_mode && (from + len < 
priv->ahbsize)) {
                if (len < 256 ||
                    dma_memcpy(buf, priv->ahbbase + from, len) < 0) {
                        memcpy_fromio(buf, priv->ahbbase + from, len);
@@ -970,7 +970,7 @@ int cadence_qspi_apb_write_execute(struct cadence_spi_priv 
*priv,
        size_t len = op->data.nbytes;
 
        cadence_qspi_apb_enable_linear_mode(true);
-       if (priv->use_dac_mode && (to + len < priv->ahbsize)) {
+       if (op->addr.nbytes && priv->use_dac_mode && (to + len < 
priv->ahbsize)) {
                memcpy_toio(priv->ahbbase + to, buf, len);
                if (!cadence_qspi_wait_idle(priv->regbase))
                        return -EIO;
-- 
2.43.2