[PATCH] clk: zynq: Fix EMIO clock use detection for gem0

[Ondřej Jirman]

From: Ondrej Jirman <m...@xff.cz>

According to TRM, the bit that differentiates between MIO and EMIO
clocks is bit 6. This resolves failure to set clock when using EMIO
clock for ethernet.

Signed-off-by: Ondrej Jirman <m...@xff.cz>
---
 drivers/clk/clk_zynq.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c
index e3cefe2e0c72..78e6886a000c 100644
--- a/drivers/clk/clk_zynq.c
+++ b/drivers/clk/clk_zynq.c
@@ -42,6 +42,8 @@
 #define CLK_CTRL_DIV3X_SHIFT   20
 #define CLK_CTRL_DIV3X_MASK    (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
 
+#define CLK_CTRL_GEM_EMIO      (1u << 6)
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SPL_BUILD
@@ -161,7 +163,7 @@ static enum zynq_clk_rclk zynq_clk_get_gem_rclk(enum 
zynq_clk id)
        else
                clk_ctrl = readl(&slcr_base->gem1_rclk_ctrl);
 
-       srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+       srcsel = (clk_ctrl & CLK_CTRL_GEM_EMIO);
        if (srcsel)
                return emio_clk;
        else
-- 
2.44.0