On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > T30+ SOC have second PLLD - PLLD2 which can be actively used by > DC and act as main DISP1/2 clock parent. > > Tested-by: Agneli <po...@protonmail.ch> # Toshiba AC100 T20 > Tested-by: Robert Eckelmann <longnose...@gmail.com> # ASUS TF101 > Tested-by: Andreas Westman Dorcsak <hed...@yahoo.com> # ASUS Grouper E1565 > Tested-by: Ion Agorria <i...@agorria.com> # HTC One X > Tested-by: Svyatoslav Ryhel <clamo...@gmail.com> # Nvidia Tegratab T114 > Signed-off-by: Svyatoslav Ryhel <clamo...@gmail.com> > --- > drivers/video/tegra20/tegra-dc.c | 6 ++++++ > 1 file changed, 6 insertions(+)
Reviewed-by: Thierry Reding <tred...@nvidia.com>
signature.asc
Description: PGP signature
