On Thu, Apr 11, 2024 at 05:29:45PM +0800, Yu Chien Peter Lin wrote: > The instruction and data cache line sizes of Andes core > are 64-byte. Select SYS_CACHE_SHIFT_6 for RISCV_NDS so > the SYS_CACHELINE_SIZE is enabled with a default value. > > Signed-off-by: Yu Chien Peter Lin <peter...@andestech.com> > --- > arch/riscv/cpu/andesv5/Kconfig | 1 + > 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Liang <ycli...@andestech.com>
