The USB3 related DT nodes in SoC u-boot.dtsi is slightly different from
the final nodes being targeted for Linux kernel v6.10.
Sync USB3 related nodes from Linux maintainer v6.10-rockchip-dts64-1 tag
to prepare for migration of RK3588 to use OF_UPSTREAM.
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
---
arch/arm/dts/rk3588-generic-u-boot.dtsi | 4 ---
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 9 +------
arch/arm/dts/rk3588-u-boot.dtsi | 36 +++++++++----------------
arch/arm/dts/rk3588s-u-boot.dtsi | 34 +++++++++--------------
4 files changed, 26 insertions(+), 57 deletions(-)
diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi
b/arch/arm/dts/rk3588-generic-u-boot.dtsi
index 225dfa0b682a..f67301d87a6e 100644
--- a/arch/arm/dts/rk3588-generic-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi
@@ -14,10 +14,6 @@
status = "okay";
};
-&usbdp_phy0_u3 {
- status = "okay";
-};
-
&usb_host0_xhci {
dr_mode = "peripheral";
maximum-speed = "high-speed";
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index 69914f4ce183..8e318e624a85 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -51,18 +51,10 @@
status = "okay";
};
-&usbdp_phy1_u3 {
- status = "okay";
-};
-
&usbdp_phy0 {
status = "okay";
};
-&usbdp_phy0_u3 {
- status = "okay";
-};
-
&usb_host0_xhci {
dr_mode = "peripheral";
maximum-speed = "high-speed";
@@ -70,5 +62,6 @@
};
&usb_host1_xhci {
+ dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi
index 992f7b5d6637..4623580c6102 100644
--- a/arch/arm/dts/rk3588-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-u-boot.dtsi
@@ -13,8 +13,8 @@
clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
<&cru ACLK_USB3OTG1>;
clock-names = "ref_clk", "suspend_clk", "bus_clk";
- dr_mode = "host";
- phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
+ dr_mode = "otg";
+ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
power-domains = <&power RK3588_PD_USB>;
@@ -32,22 +32,21 @@
};
usb2phy1_grf: syscon@fd5d4000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
- "simple-mfd";
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
reg = <0x0 0xfd5d4000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
- u2phy1: usb2-phy@4000 {
+ u2phy1: usb2phy@4000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x4000 0x10>;
- interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U3_1>, <&cru
SRST_P_USB2PHY_U3_1_GRF0>;
- reset-names = "phy", "apb";
+ #clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy1";
- #clock-cells = <0>;
+ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru
SRST_P_USB2PHY_U3_1_GRF0>;
+ reset-names = "phy", "apb";
status = "disabled";
u2phy1_otg: otg-port {
@@ -60,10 +59,7 @@
usbdp_phy1: phy@fed90000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed90000 0x0 0x10000>;
- rockchip,u2phy-grf = <&usb2phy1_grf>;
- rockchip,usb-grf = <&usb_grf>;
- rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
- rockchip,vo-grf = <&vo0_grf>;
+ #phy-cells = <1>;
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
<&cru CLK_USBDP_PHY1_IMMORTAL>,
<&cru PCLK_USBDPPHY1>,
@@ -75,16 +71,10 @@
<&cru SRST_USBDP_COMBO_PHY1_PCS>,
<&cru SRST_P_USBDPPHY1>;
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ rockchip,u2phy-grf = <&usb2phy1_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
status = "disabled";
-
- usbdp_phy1_dp: dp-port {
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usbdp_phy1_u3: usb3-port {
- #phy-cells = <0>;
- status = "disabled";
- };
};
};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index d3c257983ecb..e9d38d5c83b0 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -27,7 +27,7 @@
<&cru ACLK_USB3OTG0>;
clock-names = "ref_clk", "suspend_clk", "bus_clk";
dr_mode = "otg";
- phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
+ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
power-domains = <&power RK3588_PD_USB>;
@@ -58,22 +58,21 @@
};
usb2phy0_grf: syscon@fd5d0000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
- "simple-mfd";
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
reg = <0x0 0xfd5d0000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
- u2phy0: usb2-phy@0 {
+ u2phy0: usb2phy@0 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x0 0x10>;
- interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U3_0>, <&cru
SRST_P_USB2PHY_U3_0_GRF0>;
- reset-names = "phy", "apb";
+ #clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy0";
- #clock-cells = <0>;
+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru
SRST_P_USB2PHY_U3_0_GRF0>;
+ reset-names = "phy", "apb";
status = "disabled";
u2phy0_otg: otg-port {
@@ -91,10 +90,7 @@
usbdp_phy0: phy@fed80000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed80000 0x0 0x10000>;
- rockchip,u2phy-grf = <&usb2phy0_grf>;
- rockchip,usb-grf = <&usb_grf>;
- rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
- rockchip,vo-grf = <&vo0_grf>;
+ #phy-cells = <1>;
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
<&cru CLK_USBDP_PHY0_IMMORTAL>,
<&cru PCLK_USBDPPHY0>,
@@ -106,17 +102,11 @@
<&cru SRST_USBDP_COMBO_PHY0_PCS>,
<&cru SRST_P_USBDPPHY0>;
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ rockchip,u2phy-grf = <&usb2phy0_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
status = "disabled";
-
- usbdp_phy0_dp: dp-port {
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usbdp_phy0_u3: usb3-port {
- #phy-cells = <0>;
- status = "disabled";
- };
};
};
--
2.43.2
