[PATCH 1/2] clk: sunxi: add EMAC and EPHY clocks and resets for the V3s SoC

[Michael Walle]

Add the clock gate registers as well as the reset register bits for the
EMAC and EPHY for the V3s. These are needed by the sun8i network driver.

Signed-off-by: Michael Walle <mwa...@kernel.org>
---
 drivers/clk/sunxi/clk_v3s.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index 6524c13540e..0402d5ed190 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -17,6 +17,7 @@ static struct ccu_clk_gate v3s_gates[] = {
        [CLK_BUS_MMC0]          = GATE(0x060, BIT(8)),
        [CLK_BUS_MMC1]          = GATE(0x060, BIT(9)),
        [CLK_BUS_MMC2]          = GATE(0x060, BIT(10)),
+       [CLK_BUS_EMAC]          = GATE(0x060, BIT(17)),
        [CLK_BUS_SPI0]          = GATE(0x060, BIT(20)),
        [CLK_BUS_OTG]           = GATE(0x060, BIT(24)),
 
@@ -31,6 +32,8 @@ static struct ccu_clk_gate v3s_gates[] = {
        [CLK_BUS_UART1]         = GATE(0x06c, BIT(17)),
        [CLK_BUS_UART2]         = GATE(0x06c, BIT(18)),
 
+       [CLK_BUS_EPHY]          = GATE(0x070, BIT(0)),
+
        [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
 
        [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
@@ -45,12 +48,15 @@ static struct ccu_reset v3s_resets[] = {
        [RST_BUS_MMC0]          = RESET(0x2c0, BIT(8)),
        [RST_BUS_MMC1]          = RESET(0x2c0, BIT(9)),
        [RST_BUS_MMC2]          = RESET(0x2c0, BIT(10)),
+       [RST_BUS_EMAC]          = RESET(0x2c0, BIT(17)),
        [RST_BUS_SPI0]          = RESET(0x2c0, BIT(20)),
        [RST_BUS_OTG]           = RESET(0x2c0, BIT(24)),
 
        [RST_BUS_TCON0]         = RESET(0x2c4, BIT(4)),
        [RST_BUS_DE]            = RESET(0x2c4, BIT(12)),
 
+       [RST_BUS_EPHY]          = RESET(0x2c8, BIT(2)),
+
        [RST_BUS_I2C0]          = RESET(0x2d8, BIT(0)),
        [RST_BUS_I2C1]          = RESET(0x2d8, BIT(1)),
        [RST_BUS_UART0]         = RESET(0x2d8, BIT(16)),
-- 
2.39.2