From: Emanuele Ghidoli <emanuele.ghid...@toradex.com>
Add support for MT53E512M32D1ZW-046 IT:C memory.
This 4 GB memory has 17 row bits instead of 16 and requires 380 ns of
tRFC (tRFCab) instead of 280 ns due to increased channel density to 16 Gb.
Both modifications are retro-compatible with previous memories.
Signed-off-by: Emanuele Ghidoli <emanuele.ghid...@toradex.com>
---
board/toradex/verdin-imx8mm/lpddr4_timing.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/board/toradex/verdin-imx8mm/lpddr4_timing.c
b/board/toradex/verdin-imx8mm/lpddr4_timing.c
index 4dfec679b116..eece226b5131 100644
--- a/board/toradex/verdin-imx8mm/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mm/lpddr4_timing.c
@@ -18,7 +18,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400000, 0xa1080020},
{0x3d400020, 0x202},
{0x3d400024, 0x3a980},
- {0x3d400064, 0x2d00d2},
+ {0x3d400064, 0x2d011d},
{0x3d4000d0, 0xc00305ba},
{0x3d4000d4, 0x940000},
{0x3d4000dc, 0xd4002d},
@@ -34,7 +34,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d40011c, 0x402},
{0x3d400130, 0x20600},
{0x3d400134, 0xc100002},
- {0x3d400138, 0xd8},
+ {0x3d400138, 0x123},
{0x3d400144, 0x96004b},
{0x3d400180, 0x2ee0017},
{0x3d400184, 0x2605b8e},
@@ -56,7 +56,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400204, 0x80808},
{0x3d400214, 0x7070707},
{0x3d400218, 0x7070707},
- {0x3d40021c, 0xf0f},
+ {0x3d40021c, 0xf07},
{0x3d400250, 0x29001701},
{0x3d400254, 0x2c},
{0x3d40025c, 0x4000030},
@@ -71,7 +71,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d402020, 0x0},
{0x3d402024, 0x7d00},
{0x3d402050, 0x20d040},
- {0x3d402064, 0x6001c},
+ {0x3d402064, 0x60026},
{0x3d4020dc, 0x840000},
{0x3d4020e0, 0x310000},
{0x3d4020e8, 0x66004d},
@@ -86,7 +86,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d40211c, 0x302},
{0x3d402130, 0x20300},
{0x3d402134, 0xa100002},
- {0x3d402138, 0x1d},
+ {0x3d402138, 0x27},
{0x3d402144, 0x14000a},
{0x3d402180, 0x640004},
{0x3d402190, 0x3818200},
@@ -96,7 +96,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d403020, 0x0},
{0x3d403024, 0x1f40},
{0x3d403050, 0x20d040},
- {0x3d403064, 0x30007},
+ {0x3d403064, 0x3000A},
{0x3d4030dc, 0x840000},
{0x3d4030e0, 0x310000},
{0x3d4030e8, 0x66004d},
@@ -111,7 +111,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d40311c, 0x302},
{0x3d403130, 0x20300},
{0x3d403134, 0xa100002},
- {0x3d403138, 0x8},
+ {0x3d403138, 0xA},
{0x3d403144, 0x50003},
{0x3d403180, 0x190004},
{0x3d403190, 0x3818200},
--
2.34.1
