We might not be able to always rely on the EEPROM introspection data.
So add a config option alternative which configures the RAM size
to a fix value.
We still try to read the EEPROM introspection data at this point.
So we can print the SoM information if available.
Signed-off-by: Teresa Remmet <t.rem...@phytec.de>
---
board/phytec/phycore_imx8mp/Kconfig | 48 +++++++++++++++++++++++++++++
board/phytec/phycore_imx8mp/spl.c | 34 +++++++++++++++-----
2 files changed, 74 insertions(+), 8 deletions(-)
diff --git a/board/phytec/phycore_imx8mp/Kconfig
b/board/phytec/phycore_imx8mp/Kconfig
index f846d10bad9e..5ede39abc52b 100644
--- a/board/phytec/phycore_imx8mp/Kconfig
+++ b/board/phytec/phycore_imx8mp/Kconfig
@@ -12,5 +12,53 @@ config SYS_CONFIG_NAME
config IMX_CONFIG
default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg"
+config PHYCORE_IMX8MP_RAM_SIZE_FIX
+ bool "Set phyCORE-i.MX8MP RAM size fix instead of detecting"
+ default false
+ help
+ RAM size is automatic being detected with the help of
+ the EEPROM introspection data. Set RAM size to a fix value
+ instead.
+
+choice
+ prompt "phyCORE-i.MX8MP RAM size"
+ depends on PHYCORE_IMX8MP_RAM_SIZE_FIX
+ default PHYCORE_IMX8MP_RAM_SIZE_2GB
+
+config PHYCORE_IMX8MP_RAM_SIZE_1GB
+ bool "1GB RAM"
+ help
+ Set RAM size fix to 1GB for phyCORE-i.MX8MP.
+ RAM frequency is configured independent.
+
+config PHYCORE_IMX8MP_RAM_SIZE_2GB
+ bool "2GB RAM"
+ help
+ Set RAM size fix to 2GB for phyCORE-i.MX8MP.
+ RAM frequency is configured independent.
+
+config PHYCORE_IMX8MP_RAM_SIZE_4GB
+ bool "4GB RAM"
+ help
+ Set RAM size fix to 4GB for phyCORE-i.MX8MP.
+ RAM frequency is configured independent.
+
+config PHYCORE_IMX8MP_RAM_SIZE_8GB
+ bool "8GB RAM"
+ select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
+ help
+ Set RAM size fix to 8GB for phyCORE-i.MX8MP.
+ Only 2GHz RAMs are supported.
+
+endchoice
+
+config PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
+ bool "Use 2GHz RAM timings"
+ depends on PHYCORE_IMX8MP_RAM_SIZE_FIX
+ default false
+ help
+ Use fix 2GHz RAM timings for phyCORE-i.MX8MP instead of
+ 1.5GHz timings.
+
source "board/phytec/common/Kconfig"
endif
diff --git a/board/phytec/phycore_imx8mp/spl.c
b/board/phytec/phycore_imx8mp/spl.c
index f24f09301f1e..8a0c456859e2 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -50,20 +50,38 @@ void spl_dram_init(void)
ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
EEPROM_ADDR_FALLBACK);
- if (ret)
+ if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX))
goto out;
ret = phytec_imx8m_detect(NULL);
if (!ret)
phytec_print_som_info(NULL);
- u8 rev = phytec_get_rev(NULL);
- u8 somtype = phytec_get_som_type(NULL);
-
- if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL
&& rev >= 1)))
- use_2ghz_timings = true;
-
- size = phytec_get_imx8m_ddr_size(NULL);
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) {
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_1GB))
+ size = PHYTEC_IMX8MP_DDR_1GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_2GB))
+ size = PHYTEC_IMX8MP_DDR_2GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_4GB))
+ size = PHYTEC_IMX8MP_DDR_4GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB))
+ size = PHYTEC_IMX8MP_DDR_8GB;
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) {
+ if (size == PHYTEC_IMX8MP_DDR_4GB)
+ size = PHYTEC_IMX8MP_DDR_4GB_2GHZ;
+ else
+ use_2ghz_timings = true;
+ }
+ } else {
+ u8 rev = phytec_get_rev(NULL);
+ u8 somtype = phytec_get_som_type(NULL);
+
+ if (rev != PHYTEC_EEPROM_INVAL &&
+ (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1)))
+ use_2ghz_timings = true;
+
+ size = phytec_get_imx8m_ddr_size(NULL);
+ }
switch (size) {
case PHYTEC_IMX8MP_DDR_1GB:
--
2.34.1
