Hi Jagan,
On 2024-06-18 21:18, Jagan Teki wrote:
> On Mon, 22 Apr 2024 at 01:40, Jonas Karlman <jo...@kwiboo.se> wrote:
>>
>> The RK3328 SoC support ARMv8 Cryptography Extensions and use of the
>> ARMv8 crypto extensions help speed up FIT checksum validation in SPL.
>>
>> Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto
>> extensions for SHA256 when validating checksum of FIT images.
>>
>> Also imply OF_LIVE to help speed up init of U-Boot proper.
>>
>> Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
>> ---
>> v2: No change, rebase on latest master bransh
>> ---
>> arch/arm/mach-rockchip/Kconfig | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
>> index ee0f338995b9..651ecfe9b8fd 100644
>> --- a/arch/arm/mach-rockchip/Kconfig
>> +++ b/arch/arm/mach-rockchip/Kconfig
>> @@ -180,8 +180,11 @@ config ROCKCHIP_RK3328
>> select SUPPORT_TPL
>> select TPL
>> select TPL_NEEDS_SEPARATE_STACK if TPL
>> + imply ARMV8_CRYPTO
>> + imply ARMV8_SET_SMPEN
>
> This blocks the access of PLL registers.
>
> U-Boot 2024.07-rc4-00052-gfe2ce09a07-dirty (Jun 19 2024 - 00:43:40 +0530)
>
> Model: Firefly roc-rk3328-cc
> DRAM: 1 GiB (effective 1022 MiB)
> PMIC: RK8050 (on=0x40, off=0x00)
> Core: 241 devices, 29 uclasses, devicetree: separate
> MMC: mmc@ff500000: 1, mmc@ff520000: 0
> Loading Environment from MMC... Reading from MMC(1)... *** Warning -
> bad CRC, using default environment
>
> inno_hdmi_phy phy@ff430000: Pre-PLL locking failed
> inno_hdmi_phy phy@ff430000: PHY: Failed to power on phy@ff430000: -110.
> failed to power on phy (ret=-110)
> inno_hdmi_phy phy@ff430000: Pre-PLL locking failed
> inno_hdmi_phy phy@ff430000: PHY: Failed to power on phy@ff430000: -110.
> failed to power on phy (ret=-110)
> In: serial,usbkbd
> Out: serial,vidconsole
> Err: serial,vidconsole
> Model: Firefly roc-rk3328-cc
> Net: eth0: ethernet@ff540000
I could reproduce this issue on my Rock64, and it looks like there is a
bug in inno phy driver at inno_poll, it currently readl at wrong addr:
---
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index 3bb1a254ffb5..7459779dffed 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -432,8 +432,8 @@ static inline void inno_update_bits(struct inno_hdmi_phy
*inno, u8 reg,
inno_write(inno, reg, tmp);
}
-#define inno_poll(reg, val, cond, sleep_us, timeout_us) \
- readl_poll_sleep_timeout((reg) * 4, val, cond, sleep_us, timeout_us)
+#define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \
+ readl_poll_sleep_timeout((inno)->regs + ((reg) * 4), val, cond,
sleep_us, timeout_us)
static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno,
unsigned long rate)
@@ -575,7 +575,7 @@ inno_hdmi_phy_rk3328_clk_set_rate(struct phy *phy,
inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
/* Wait for Pre-PLL lock */
- ret = inno_poll(0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS,
+ ret = inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS,
1000, 10000);
if (ret) {
dev_err(phy->dev, "Pre-PLL locking failed\n");
@@ -674,7 +674,7 @@ inno_hdmi_phy_rk3328_power_on(struct phy *phy,
RK3328_TMDS_DRIVER_ENABLE);
/* Wait for post PLL lock */
- ret = inno_poll(0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS,
+ ret = inno_poll(inno, 0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS,
1000, 10000);
if (ret) {
dev_err(phy->dev, "Post-PLL locking failed\n");
---
Please send a proper patch to fix inno_poll :-)
Regards,
Jonas
>
> Jagan.
