Hi Philip,
On Mon, 24 Jun 2024 at 02:35, Philip Oberfichtner <p...@denx.de> wrote:
>
> Implement memory barrier using mfence. Linux does it equivalently [1].
>
> "The MFENCE instruction establishes a memory fence for both loads and
> stores" [2].
>
> [1] linux/arch/x86/include/asm/barrier.h
> [2] Intel® 64 and IA-32 Architectures Software Developer’s Manual
>
> Signed-off-by: Philip Oberfichtner <p...@denx.de>
> ---
> arch/x86/include/asm/io.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
> index 5efb2e1b21..936ad6f588 100644
> --- a/arch/x86/include/asm/io.h
> +++ b/arch/x86/include/asm/io.h
> @@ -244,6 +244,7 @@ static inline void sync(void)
> * have some advantages to use them instead of the simple one here.
> */
> #define dmb() __asm__ __volatile__ ("" : : : "memory")
> +#define mb() __asm__ __volatile__ ("mfence" : : : "memory")
> #define __iormb() dmb()
> #define __iowmb() dmb()
>
> --
This exists in arch/x86/include/asm/cpu.h so can you please remove
that one as well, in this patch?
Regards,
Simon
> 2.39.2
>
