This patch only shows the problem on an existing platform. Turning on the cadence QSPI flash breaks the build for arria10. Can you reproduce?
make socfpga_arria10_defconfig make Signed-off-by: Lothar Rubusch <l.rubu...@gmail.com> --- NB: Don't apply this config/patch permanently! The Cadence QSPI flash can be tricky due to a write reset register instruction which can brick the board if interrupted. We experienced this situation. So, that's why I removed the config option in my boards (to be upstreamed soon). Hence, my boards won't show the above problem anymore. Anyway, I think the code section in misc_arria10.c have a bug. So, I presented the before patch. --- configs/socfpga_arria10_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 6d27deeb..c7321bab 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -61,6 +61,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_DESIGNWARE_APB_TIMER=y -- 2.25.1
