Re: [PATCH RFC v2 22/23] sysreset: rockchip: use fst reset for ARM64 SOC

[Kever Yang]

On 2024/6/1 00:44, Jonas Karlman wrote:
Hi Anand and Kever,

On 2024-05-31 16:18, Anand Moon wrote:
From: Kever Yang <kever.y...@rock-chips.com>

Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.
What is this trying to fix? And what SoCs is affected?

Both fst and snd softreset are available for SoCs, but the fst reset 
more thing.

This commit msg is about: in some case the CPU entry may change after 
system boot,

eg. the wakeup code for deep sleep mode(which may power off) is locate 
at a different address;

with fst reset, the CPU entry is reset to the one bootRom used but the 
snd reset can not.

All the mass produced product with ARM64 SoCs are using the first global 
reset for warn reset now.


Thanks,
- Kever
My arm64 RK SoCs seem to reset using warm reset (second global reset).

Cc: Jagan Teki <ja...@edgeble.ai>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
  drivers/sysreset/sysreset_rockchip.c | 5 +++++
  1 file changed, 5 insertions(+)

diff --git a/drivers/sysreset/sysreset_rockchip.c 
b/drivers/sysreset/sysreset_rockchip.c
index f353f9b4c7..17aa191349 100644
--- a/drivers/sysreset/sysreset_rockchip.c
+++ b/drivers/sysreset/sysreset_rockchip.c
@@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev, enum 
sysreset_t type)
  
  	switch (type) {
        case SYSRESET_WARM:
+#ifdef CONFIG_ARM64
+               /* Rockchip 64bit SOC need fst reset for cpu reset entry */
+               writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
+#else
                writel(0xeca8, cru_base + offset->glb_srst_snd_value);
+#endif
If this is needed maybe use something like this and let it fall through
to SYSRESET_COLD?

   if (!IS_ENABLED(CONFIG_ARM64)) {
        writel(0xeca8, cru_base + offset->glb_srst_snd_value);
        break;
   }

Regards,
Jonas

                break;
        case SYSRESET_COLD:
                writel(0xfdb9, cru_base + offset->glb_srst_fst_value);