Re: [PATCH 37/37] board: xilinx: Remove duplicate newlines

[Michal Simek]

On 7/19/24 12:49, Marek Vasut wrote:

Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+rene...@mailbox.org>
---
  board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c | 2 --
  board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c    | 2 --
  board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c    | 2 --
  board/xilinx/zynq/zynq-zed/ps7_init_gpl.c      | 2 --
  board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c     | 3 ---
  5 files changed, 11 deletions(-)

diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c 
b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
index 602a789e775..e7f1d6ef5ec 100644
--- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
@@ -4060,7 +4060,6 @@ unsigned long ps7_post_config_3_0[] = {
      //
  };

-

  unsigned long ps7_pll_init_data_2_0[] = {
      // START: top
      // .. START: SLCR SETTINGS
@@ -8263,7 +8262,6 @@ unsigned long ps7_post_config_2_0[] = {
      //
  };

-

  unsigned long ps7_pll_init_data_1_0[] = {
      // START: top
      // .. START: SLCR SETTINGS
diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c 
b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
index 9343683f4d7..48001269cd7 100644
--- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
@@ -4167,7 +4167,6 @@ unsigned long ps7_post_config_3_0[] = {
      //
  };

-

  unsigned long ps7_pll_init_data_2_0[] = {
      // START: top
      // .. START: SLCR SETTINGS
@@ -8483,7 +8482,6 @@ unsigned long ps7_post_config_2_0[] = {
      //
  };

-

  unsigned long ps7_pll_init_data_1_0[] = {
      // START: top
      // .. START: SLCR SETTINGS
diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c 
b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
index 6b153aa3796..76ef5d9323e 100644
--- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
@@ -4136,7 +4136,6 @@ unsigned long ps7_post_config_3_0[] = {
      //
  };

-

  unsigned long ps7_pll_init_data_2_0[] = {
      // START: top
      // .. START: SLCR SETTINGS
@@ -8421,7 +8420,6 @@ unsigned long ps7_post_config_2_0[] = {
      //
  };

-

  unsigned long ps7_pll_init_data_1_0[] = {
      // START: top
      // .. START: SLCR SETTINGS
diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c 
b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
index 6f2edf16c24..67642798b41 100644
--- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
@@ -4026,7 +4026,6 @@ unsigned long ps7_post_config_3_0[] = {
      //
  };

-

  unsigned long ps7_pll_init_data_2_0[] = {
      // START: top
      // .. START: SLCR SETTINGS
@@ -8195,7 +8194,6 @@ unsigned long ps7_post_config_2_0[] = {
      //
  };

-

  unsigned long ps7_pll_init_data_1_0[] = {
      // START: top
      // .. START: SLCR SETTINGS
diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c 
b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
index 04d2e5f1375..6a3236ce2d2 100644
--- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
@@ -4082,7 +4082,6 @@ unsigned long ps7_post_config_3_0[] = {
        /* */
  };

-

  unsigned long ps7_pll_init_data_2_0[] = {
        /* START: top */
        /* .. START: SLCR SETTINGS */
@@ -8313,7 +8312,6 @@ unsigned long ps7_post_config_2_0[] = {
        /* */
  };

-

  unsigned long ps7_pll_init_data_1_0[] = {
        /* START: top */
        /* .. START: SLCR SETTINGS */
@@ -12477,7 +12475,6 @@ unsigned long ps7_post_config_1_0[] = {
        /* */
  };

-

  #include "xil_io.h"

unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;

Reviewed-by: Michal Simek <michal.si...@amd.com>

Thanks,
Michal

--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs