Hi Mike,
> + ds->slave.bus = bus;
> > + ds->slave.cs = cs;
> > + ds->regs = (struct andes_spi_regs *)CONFIG_SYS_SPI_BASE;
> > + ds->freq = max_hz;
>
>
your spi controller has no frequency limit ? your spi_claim_bus
> indicates that there is ...
>
>
Hey, it really strange but I couldn't help. ;p
According to the hardware datasheet, the only thing related to frequence is
baudrate.
But, any value I set to baudrate was no affect.
It seems that something has done between the hardware itselves.
I've asked the designer and he said the software coder should not care about
this.
> > +static int andes_spi_read(struct spi_slave *slave, unsigned int len,
> > + u8 *rxp, unsigned long flags)
> > +{
> > ....
> > + while (len > 0) {
> > + debug(" ");
> > + if (len / 4 > 0)
> > + left = 4;
> > + else
> > + left = len;
>
> seems like you want:
> left = max(len, 4);
>
No. Since the hardware is really designed so strange.
Although the data of SPI should be transfered byte-by-bytes.
But this hardware requires you put the data 32bit (a register's length)
once.
So, If you exactly have a data more then 4 bytes, you must have to divide
them
into 4 bytes a chunk, and write them 4 bytes a time.
That's why left = max(len, 4) doesn't help. The value of left cannot larger
than 4.
> > + data = readl(&ds->regs->data);
> > + for (i = 0; i < left; i++) {
> > + debug("%02x ", data & 0xff);
> > + *rxp++ = data;
> > + data >>= 8;
> > + len--;
> > + }
> > + }
>
> looks to me like you write too much data ... if someone does a spi
> read of 1 byte, you still write out 4 ?
>
>
Same problem here. This SPI interface must read and write 4 byte a time.
The hardware designer thinks they are really smart.
The hardware will strip the padding according to the data lenght in
"WRITEthenREAD" command.
Thanks.
I'll fix the rest of those problem and send patch v2.
--
Best regards,
Macpaul Lin
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