Hi,
On Thu, 29 Aug 2024 at 07:01, Minda Chen <minda.c...@starfivetech.com> wrote:
>
> Add Jh7110 Cadence USB dts node, Visionfive2 default setting
> is USB 2.0 device.
>
> Signed-off-by: Minda Chen <minda.c...@starfivetech.com>
> ---
> .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> arch/riscv/dts/jh7110.dtsi | 53 +++++++++++++++++++
> 2 files changed, 58 insertions(+)
Can you try to evaluate if this SoC can support OF_UPSTREAM? I can see
corresponding DT sources well supported by dts/upstream. AFAICS, you
at least need to add a Makefile for RISC-V here:
dts/upstream/src/riscv/ for which you can reference
dts/upstream/src/arm64/Makefile.
This is not something to be considered as a blocker for this series
but kind of follow-up work.
-Sumit
>
> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> index e11babc1cd..44785bbee3 100644
> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> @@ -378,3 +378,8 @@
> };
> };
> };
> +
> +&usb_cdns3 {
> + dr_mode = "peripheral";
> + status = "okay";
> +};
> diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
> index 2cdc683d49..7bf9b2a03a 100644
> --- a/arch/riscv/dts/jh7110.dtsi
> +++ b/arch/riscv/dts/jh7110.dtsi
> @@ -371,6 +371,59 @@
> status = "disabled";
> };
>
> + usb0: usb@10100000 {
> + compatible = "starfive,jh7110-usb";
> + ranges = <0x0 0x0 0x10100000 0x100000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + starfive,stg-syscon = <&stg_syscon 0x4>;
> + clocks = <&stgcrg JH7110_STGCLK_USB_LPM>,
> + <&stgcrg JH7110_STGCLK_USB_STB>,
> + <&stgcrg JH7110_STGCLK_USB_APB>,
> + <&stgcrg JH7110_STGCLK_USB_AXI>,
> + <&stgcrg JH7110_STGCLK_USB_UTMI_APB>;
> + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
> + resets = <&stgcrg JH7110_STGRST_USB_PWRUP>,
> + <&stgcrg JH7110_STGRST_USB_APB>,
> + <&stgcrg JH7110_STGRST_USB_AXI>,
> + <&stgcrg JH7110_STGRST_USB_UTMI_APB>;
> + reset-names = "pwrup", "apb", "axi", "utmi_apb";
> +
> + usb_cdns3: usb@0 {
> + compatible = "cdns,usb3";
> + reg = <0x0 0x10000>,
> + <0x10000 0x10000>,
> + <0x20000 0x10000>;
> + reg-names = "otg", "xhci", "dev";
> + interrupts = <100>, <108>, <110>;
> + interrupt-names = "host", "peripheral", "otg";
> + phys = <&usbphy0>;
> + phy-names = "cdns3,usb2-phy";
> + };
> + };
> +
> + usbphy0: phy@10200000 {
> + compatible = "starfive,jh7110-usb-phy";
> + reg = <0x0 0x10200000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
> + <&stgcrg JH7110_STGCLK_USB_APP_125>;
> + clock-names = "125m", "app_125m";
> + starfive,sys-syscon = <&sys_syscon 0x18>;
> + #phy-cells = <0>;
> + };
> +
> + pciephy0: phy@10210000 {
> + compatible = "starfive,jh7110-pcie-phy";
> + reg = <0x0 0x10210000 0x0 0x10000>;
> + #phy-cells = <0>;
> + };
> +
> + pciephy1: phy@10220000 {
> + compatible = "starfive,jh7110-pcie-phy";
> + reg = <0x0 0x10220000 0x0 0x10000>;
> + #phy-cells = <0>;
> + };
> +
> stgcrg: clock-controller@10230000 {
> compatible = "starfive,jh7110-stgcrg";
> reg = <0x0 0x10230000 0x0 0x10000>;
> --
> 2.17.1
>
