On Wed, 18 Sept 2024 at 17:25, Patrick Rudolph
<patrick.rudo...@9elements.com> wrote:
>
> Add a generic GICV2 driver that:
> - parses the DT and generates the ACPI MADT subtables
> - implement of_xlate() and allows irq_get_by_index() to return the
> correct interrupt mappings
>
> TEST: Booted on QEMU raspb4 using GICV2 driver model generated MADT.
>
> Signed-off-by: Patrick Rudolph <patrick.rudo...@9elements.com>
> ---
> arch/arm/Kconfig | 7 ++++
> arch/arm/lib/Makefile | 1 +
> arch/arm/lib/gic-v2.c | 89 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 97 insertions(+)
> create mode 100644 arch/arm/lib/gic-v2.c
Reviewed-by: Simon Glass <s...@chromium.org>
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index ba0359fed5..50327f5349 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -113,6 +113,13 @@ config GICV2
> config GICV3
> bool
>
> +config DRIVER_GICV2
> + bool "ARM GICV2 driver"
> + select IRQ
> + help
> + ARM GICV2 driver.
> + Basic support for parsing the GICV2 node and generate ACPI tables.
s/for parsing/to parse/
or change generate to generating
> +
> config GIC_V3_ITS
> bool "ARM GICV3 ITS"
> select IRQ
> diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
> index a7efed6771..cf76051450 100644
> --- a/arch/arm/lib/Makefile
> +++ b/arch/arm/lib/Makefile
> @@ -68,6 +68,7 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += ccn504.o
> ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),)
> obj-y += gic_64.o
> endif
> +obj-$(CONFIG_DRIVER_GICV2) += gic-v2.o
> obj-$(CONFIG_GIC_V3_ITS) += gic-v3-its.o
> obj-y += interrupts_64.o
> else
> diff --git a/arch/arm/lib/gic-v2.c b/arch/arm/lib/gic-v2.c
> new file mode 100644
> index 0000000000..c9f9f441eb
> --- /dev/null
> +++ b/arch/arm/lib/gic-v2.c
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 Broadcom.
> + */
> +#include <asm/gic.h>
> +#include <asm/acpi_table.h>
> +#include <cpu_func.h>
> +#include <dm/acpi.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
Please check header-file order in all your patches.
> +#include <dm.h>
> +#include <irq.h>
> +
> +#ifdef CONFIG_ACPIGEN
> +/**
> + * acpi_gicv2_fill_madt() - Fill out the body of the MADT
> + *
> + * Write GICD and GICR tables based on collected devicetree data.
> + *
> + * @dev: Device to write ACPI tables for
> + * @ctx: ACPI context to write MADT sub-tables to
> + * Return: 0 if OK
> + */
> +static int acpi_gicv2_fill_madt(const struct udevice *dev, struct acpi_ctx
> *ctx)
> +{
> + struct acpi_madt_gicd *gicd;
> + fdt_addr_t addr;
> +
> + addr = dev_read_addr_index(dev, 0);
> + if (addr == FDT_ADDR_T_NONE) {
> + pr_err("%s: failed to get GICD address\n", __func__);
> + return -EINVAL;
> + }
> +
> + gicd = ctx->current;
> + acpi_write_madt_gicd(gicd, dev_seq(dev), addr, 2);
> + acpi_inc(ctx, gicd->length);
> +
> + return 0;
> +}
> +
> +static struct acpi_ops gic_v2_acpi_ops = {
> + .fill_madt = acpi_gicv2_fill_madt,
> +};
> +#endif
> +
> +static const struct udevice_id gic_v2_ids[] = {
> + { .compatible = "arm,arm11mp-gic" },
> + { .compatible = "arm,cortex-a15-gic" },
> + { .compatible = "arm,cortex-a7-gic" },
> + { .compatible = "arm,cortex-a5-gic" },
> + { .compatible = "arm,cortex-a9-gic" },
> + { .compatible = "arm,eb11mp-gic" },
> + { .compatible = "arm,gic-400" },
> + { .compatible = "arm,pl390" },
> + { .compatible = "arm,tc11mp-gic" },
> + { .compatible = "qcom,msm-8660-qgic" },
> + { .compatible = "qcom,msm-qgic2" },
> + {}
> +};
> +
> +static int arm_gic_v2_of_xlate(struct irq *irq, struct ofnode_phandle_args
> *args)
> +{
> + if (args->args_count != 3) {
> + log_debug("Invalid args_count: %d\n", args->args_count);
> + return -EINVAL;
> + }
> +
> + /* ARM Generic Interrupt Controller v1 and v2 */
> + if (args->args[0] == GIC_PPI)
> + irq->id = args->args[1] + 16;
> + else
> + irq->id = args->args[1];
> +
> + irq->flags = args->args[2];
> +
> + return 0;
> +}
> +
> +static const struct irq_ops arm_gic_v2_ops = {
> + .of_xlate = arm_gic_v2_of_xlate,
> +};
> +
> +U_BOOT_DRIVER(arm_gic_v2) = {
> + .name = "gic-v2",
> + .id = UCLASS_IRQ,
> + .of_match = gic_v2_ids,
> + .ops = &arm_gic_v2_ops,
> + ACPI_OPS_PTR(&gic_v2_acpi_ops)
> +};
> --
> 2.46.0
>
Regards,
Simon
