The SSCG is active with MDSEL[12] is not set. Previous commit
99c7e031196d ("clk: renesas: rcar-gen3: Replace SSCG caching
with MDSEL/PE caching") inverted the conditional assignment
of priv->sscg = !(cpg_mode & BIT(12)) during conversion from
(priv->sscg ? 16 : 0) to priv->cpg_mode & BIT(core->offset) ? 16 : 0;
Invert the assignment back to the correct state.
This fixes R8A77980, R8A77990, R8A77995 and R8A774C0.
Fixes: 99c7e031196d ("clk: renesas: rcar-gen3: Replace SSCG caching with
MDSEL/PE caching")
Signed-off-by: Marek Vasut <[email protected]>
---
Cc: Tom Rini <[email protected]>
---
NOTE: This is for 2024.10
---
drivers/clk/renesas/clk-rcar-gen3.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index ac05788ccc5..aa38c0f7dd0 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -69,7 +69,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv,
struct clk *clk,
return ret;
if (core->type == CLK_TYPE_GEN3_MDSEL) {
- shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
+ shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
parent->dev = clk->dev;
parent->id = core->parent >> shift;
parent->id &= 0xffff;
@@ -318,7 +318,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
"FIXED");
case CLK_TYPE_GEN3_MDSEL:
- shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
+ shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16;
div = (core->div >> shift) & 0xffff;
rate = gen3_clk_get_rate64(&parent) / div;
debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
--
2.45.2
