On 05/19/2011 06:32 PM, Fabio Estevam wrote: > MX51EVK board has 2 banks of 256MB DDR memories instead of a single one with > 512MB. > > Signed-off-by: Fabio Estevam <fabio.este...@freescale.com> > ---
Hi Fabio, > board/freescale/mx51evk/mx51evk.c | 18 +++++++++++++++--- > include/configs/mx51evk.h | 7 +++++-- > 2 files changed, 20 insertions(+), 5 deletions(-) > > diff --git a/board/freescale/mx51evk/mx51evk.c > b/board/freescale/mx51evk/mx51evk.c > index e2d3d74..ef7c6e4 100644 > --- a/board/freescale/mx51evk/mx51evk.c > +++ b/board/freescale/mx51evk/mx51evk.c > @@ -52,11 +52,23 @@ u32 get_board_rev(void) > > int dram_init(void) > { > - /* dram_init must store complete ramsize in gd->ram_size */ > - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, > - PHYS_SDRAM_1_SIZE); > + u32 size1, size2; > + > + size1 = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); > + size2 = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); > + > + gd->ram_size = size1 + size2; > + Do we really need this patch ? I am trying to understand. I think we need always to set up two (or more) banks if there is a hole between the two banks. For example, if it would be possible to install a memory with a smaller size. This is the case of the MX53loco, because the range between CSD0 and CSD1 is 1GB. This is not the case of the mx51evk, if I am correct. CSD0 and CSD1 address each 256MB, and memory from the software point of view is contiguous. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de ===================================================================== _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot