Hi Prafulla, Please, consider adding this patch to the current release.
Thanks in advance. Simon On Tue, May 17, 2011 at 02:42:10PM +0200, Simon Guinot wrote: > This patch add support for the Network Space v2 board and parents, based > on the Marvell Kirkwood 6281 SoC. This include Network Space (Max) v2 > and Internet Space v2. > > Additional information is available at: > http://lacie-nas.org/doku.php?id=network_space_v2 > > Signed-off-by: Simon Guinot <sgui...@lacie.com> > --- > Changes for v2: > - add entries to MAINTAINERS file > - move boards from root Makefile to boards.cfg > - move MACH_TYPE definition into netspace_v2.h > - remove CONFIG_SYS_HZ redefinition > - turn PHY initialization message into debug() > > Changes for v3: none > > Changes for v4: > - enhance commit message: add SoC information > > Changes for v5: none > > Changes for v6: > - enable device tree support > - clean some "#define" in netspace_v2.h > - enhance commit message: provide description URL and mention SoC > family > - rebase against u-boot-{arm,marvell}/master branches > > Changes for v7: > - rebase against u-boot-marvell/master branch > > Changes for v8: > - update commit title (add netspace_v2 parents information). > - move GPIO button definition into header file. > - update CONFIG_IDENT_STRING with boards alias. > - handle wrong board definition. > - by default, use DHCP to get IP address. > > Changes for v9: > - rebase against u-boot-marvell/master branch > > MAINTAINERS | 6 + > board/LaCie/netspace_v2/Makefile | 49 ++++++++++ > board/LaCie/netspace_v2/kwbimage.cfg | 162 > +++++++++++++++++++++++++++++++++ > board/LaCie/netspace_v2/netspace_v2.c | 142 +++++++++++++++++++++++++++++ > board/LaCie/netspace_v2/netspace_v2.h | 42 +++++++++ > boards.cfg | 3 + > include/configs/netspace_v2.h | 162 > +++++++++++++++++++++++++++++++++ > 7 files changed, 566 insertions(+), 0 deletions(-) > create mode 100644 board/LaCie/netspace_v2/Makefile > create mode 100644 board/LaCie/netspace_v2/kwbimage.cfg > create mode 100644 board/LaCie/netspace_v2/netspace_v2.c > create mode 100644 board/LaCie/netspace_v2/netspace_v2.h > create mode 100644 include/configs/netspace_v2.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index 24a55c2..47b724c 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -645,6 +645,12 @@ Sedji Gaouaou<sedji.gaou...@atmel.com> > at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC) > at91sam9m10g45ek ARM926EJS (AT91SAM9G45 SoC) > > +Simon Guinot <simon.gui...@sequanux.org> > + > + inetspace_v2 ARM926EJS (Kirkwood SoC) > + netspace_v2 ARM926EJS (Kirkwood SoC) > + netspace_max_v2 ARM926EJS (Kirkwood SoC) > + > Marius Gr?ger <m...@sysgo.de> > > impa7 ARM720T (EP7211) > diff --git a/board/LaCie/netspace_v2/Makefile > b/board/LaCie/netspace_v2/Makefile > new file mode 100644 > index 0000000..a245f2c > --- /dev/null > +++ b/board/LaCie/netspace_v2/Makefile > @@ -0,0 +1,49 @@ > +# > +# Copyright (C) 2011 Simon Guinot <sgui...@lacie.com> > +# > +# Based on Kirkwood support: > +# (C) Copyright 2009 > +# Marvell Semiconductor <www.marvell.com> > +# Written-by: Prafulla Wadaskar <prafu...@marvell.com> > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(BOARD).o > + > +COBJS := netspace_v2.o > + > +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS)) > +SOBJS := $(addprefix $(obj),$(SOBJS)) > + > +$(LIB): $(obj).depend $(OBJS) $(SOBJS) > + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) > + > +clean: > + rm -f $(SOBJS) $(OBJS) > + > +distclean: clean > + rm -f $(LIB) core *.bak .depend > + > +######################################################################### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > diff --git a/board/LaCie/netspace_v2/kwbimage.cfg > b/board/LaCie/netspace_v2/kwbimage.cfg > new file mode 100644 > index 0000000..361feeb > --- /dev/null > +++ b/board/LaCie/netspace_v2/kwbimage.cfg > @@ -0,0 +1,162 @@ > +# > +# Copyright (C) 2011 Simon Guinot <sgui...@lacie.com> > +# > +# Based on Kirkwood support: > +# (C) Copyright 2009 > +# Marvell Semiconductor <www.marvell.com> > +# Written-by: Prafulla Wadaskar <prafu...@marvell.com> > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# Refer docs/README.kwimage for more details about how-to configure > +# and create kirkwood boot image > +# > + > +# Boot Media configurations > +BOOT_FROM spi # Boot from SPI flash > + > +# SOC registers configuration using bootrom header extension > +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed > + > +# Configure RGMII-0 interface pad voltage to 1.8V > +DATA 0xFFD100e0 0x1B1B1B9B > + > +#Dram initalization for SINGLE x16 CL=5 @ 400MHz > +DATA 0xFFD01400 0x43000618 # DDR Configuration register > +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) > +# bit23-14: zero > +# bit24: 1= enable exit self refresh mode on DDR access > +# bit25: 1 required > +# bit29-26: zero > +# bit31-30: 01 > + > +DATA 0xFFD01404 0x35143000 # DDR Controller Control Low > +# bit 4: 0=addr/cmd in smame cycle > +# bit 5: 0=clk is driven during self refresh, we don't care for APX > +# bit 6: 0=use recommended falling edge of clk for addr/cmd > +# bit14: 0=input buffer always powered up > +# bit18: 1=cpu lock transaction enabled > +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 > +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered > DIMM > +# bit30-28: 3 required > +# bit31: 0=no additional STARTBURST delay > + > +DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) > +# bit7-4: TRCD > +# bit11- 8: TRP > +# bit15-12: TWR > +# bit19-16: TWTR > +# bit20: TRAS msb > +# bit23-21: 0x0 > +# bit27-24: TRRD > +# bit31-28: TRTP > + > +DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) > +# bit6-0: TRFC > +# bit8-7: TR2R > +# bit10-9: TR2W > +# bit12-11: TW2W > +# bit31-13: zero required > + > +DATA 0xFFD01410 0x0000CCCC # DDR Address Control > +# bit1-0: 01, Cs0width=x16 > +# bit3-2: 11, Cs0size=1Gb > +# bit5-4: 00, Cs2width=nonexistent > +# bit7-6: 00, Cs1size =nonexistent > +# bit9-8: 00, Cs2width=nonexistent > +# bit11-10: 00, Cs2size =nonexistent > +# bit13-12: 00, Cs3width=nonexistent > +# bit15-14: 00, Cs3size =nonexistent > +# bit16: 0, Cs0AddrSel > +# bit17: 0, Cs1AddrSel > +# bit18: 0, Cs2AddrSel > +# bit19: 0, Cs3AddrSel > +# bit31-20: 0 required > + > +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control > +# bit0: 0, OpenPage enabled > +# bit31-1: 0 required > + > +DATA 0xFFD01418 0x00000000 # DDR Operation > +# bit3-0: 0x0, DDR cmd > +# bit31-4: 0 required > + > +DATA 0xFFD0141C 0x00000632 # DDR Mode > +# bit2-0: 2, BurstLen=2 required > +# bit3: 0, BurstType=0 required > +# bit6-4: 4, CL=5 > +# bit7: 0, TestMode=0 normal > +# bit8: 0, DLL reset=0 normal > +# bit11-9: 6, auto-precharge write recovery ???????????? > +# bit12: 0, PD must be zero > +# bit31-13: 0 required > + > +DATA 0xFFD01420 0x00000004 # DDR Extended Mode > +# bit0: 0, DDR DLL enabled > +# bit1: 1, DDR drive strenght reduced > +# bit2: 1, DDR ODT control lsd enabled > +# bit5-3: 000, required > +# bit6: 1, DDR ODT control msb, enabled > +# bit9-7: 000, required > +# bit10: 0, differential DQS enabled > +# bit11: 0, required > +# bit12: 0, DDR output buffer enabled > +# bit31-13: 0 required > + > +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High > +# bit2-0: 111, required > +# bit3 : 1 , MBUS Burst Chop disabled > +# bit6-4: 111, required > +# bit7 : 1 , D2P Latency enabled > +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz > +# bit9 : 0 , no half clock cycle addition to dataout > +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals > +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh > +# bit15-12: 1111 required > +# bit31-16: 0 required > + > +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) > +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) > + > +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 > +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size > +# bit0: 1, Window enabled > +# bit1: 0, Write Protect disabled > +# bit3-2: 00, CS0 hit selected > +# bit23-4: ones, required > +# bit31-24: 0x07, Size (i.e. 128MB) > + > +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled > +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled > +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled > + > +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) > +# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 > +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 > + > +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) > +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above > +# bit3-2: 01, ODT1 active NEVER! > +# bit31-4: zero, required > + > +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control > +# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 > +# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 > +# bit11-10:1, DQ_ODTSel. ODT select turned on > + > +DATA 0xFFD01480 0x00000001 # DDR Initialization Control > +#bit0=1, enable DDR init upon this register write > + > +# End of Header extension > +DATA 0x0 0x0 > diff --git a/board/LaCie/netspace_v2/netspace_v2.c > b/board/LaCie/netspace_v2/netspace_v2.c > new file mode 100644 > index 0000000..3bb83f3 > --- /dev/null > +++ b/board/LaCie/netspace_v2/netspace_v2.c > @@ -0,0 +1,142 @@ > +/* > + * Copyright (C) 2011 Simon Guinot <sgui...@lacie.com> > + * > + * Based on Kirkwood support: > + * (C) Copyright 2009 > + * Marvell Semiconductor <www.marvell.com> > + * Written-by: Prafulla Wadaskar <prafu...@marvell.com> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <common.h> > +#include <miiphy.h> > +#include <netdev.h> > +#include <command.h> > +#include <asm/arch/kirkwood.h> > +#include <asm/arch/mpp.h> > +#include <asm/arch/gpio.h> > +#include "netspace_v2.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int board_early_init_f(void) > +{ > + /* Gpio configuration */ > + kw_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH, > + NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH); > + > + /* Multi-Purpose Pins Functionality configuration */ > + u32 kwmpp_config[] = { > + MPP0_SPI_SCn, > + MPP1_SPI_MOSI, > + MPP2_SPI_SCK, > + MPP3_SPI_MISO, > + MPP4_NF_IO6, > + MPP5_NF_IO7, > + MPP6_SYSRST_OUTn, > + MPP7_GPO, /* Fan speed (bit 1) */ > + MPP8_TW_SDA, > + MPP9_TW_SCK, > + MPP10_UART0_TXD, > + MPP11_UART0_RXD, > + MPP12_GPO, /* Red led */ > + MPP14_GPIO, /* USB fuse */ > + MPP16_GPIO, /* SATA 0 power */ > + MPP17_GPIO, /* SATA 1 power */ > + MPP18_NF_IO0, > + MPP19_NF_IO1, > + MPP20_SATA1_ACTn, > + MPP21_SATA0_ACTn, > + MPP22_GPIO, /* Fan speed (bit 0) */ > + MPP23_GPIO, /* Fan power */ > + MPP24_GPIO, /* USB mode select */ > + MPP25_GPIO, /* Fan rotation fail */ > + MPP26_GPIO, /* USB vbus-in detection */ > + MPP28_GPIO, /* USB enable vbus-out */ > + MPP29_GPIO, /* Blue led (slow register) */ > + MPP30_GPIO, /* Blue led (command register) */ > + MPP31_GPIO, /* Board power off */ > + MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */ > + MPP33_GPIO, /* Fan speed (bit 2) */ > + 0 > + }; > + kirkwood_mpp_conf(kwmpp_config); > + > + return 0; > +} > + > +int board_init(void) > +{ > + /* Machine number */ > + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; > + > + /* Boot parameters address */ > + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; > + > + return 0; > +} > + > +void mv_phy_88e1116_init(char *name) > +{ > + u16 reg; > + u16 devadr; > + > + if (miiphy_set_current_dev(name)) > + return; > + > + /* command to read PHY dev address */ > + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { > + printf("Err..(%s) could not read PHY dev address\n", __func__); > + return; > + } > + > + /* > + * Enable RGMII delay on Tx and Rx for CPU port > + * Ref: sec 4.7.2 of chip datasheet > + */ > + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); > + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); > + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); > + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); > + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); > + > + /* reset the phy */ > + if (miiphy_read(name, devadr, MII_BMCR, ®) != 0) { > + printf("Err..(%s) PHY status read failed\n", __func__); > + return; > + } > + if (miiphy_write(name, devadr, MII_BMCR, reg | 0x8000) != 0) { > + printf("Err..(%s) PHY reset failed\n", __func__); > + return; > + } > + > + debug("88E1116 Initialized on %s\n", name); > +} > + > +/* Configure and initialize PHY */ > +void reset_phy(void) > +{ > + mv_phy_88e1116_init("egiga0"); > +} > + > +/* Return GPIO button status */ > +static int > +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) > +{ > + return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON); > +} > + > +U_BOOT_CMD(button, 1, 1, do_read_button, > + "Return GPIO button status 0=off 1=on", ""); > diff --git a/board/LaCie/netspace_v2/netspace_v2.h > b/board/LaCie/netspace_v2/netspace_v2.h > new file mode 100644 > index 0000000..3f3d51c > --- /dev/null > +++ b/board/LaCie/netspace_v2/netspace_v2.h > @@ -0,0 +1,42 @@ > +/* > + * Copyright (C) 2011 Simon Guinot <sgui...@lacie.com> > + * > + * Based on Kirkwood support: > + * (C) Copyright 2009 > + * Marvell Semiconductor <www.marvell.com> > + * Written-by: Prafulla Wadaskar <prafu...@marvell.com> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#ifndef NETSPACE_V2_H > +#define NETSPACE_V2_H > + > +/* GPIO configuration */ > +#define NETSPACE_V2_OE_LOW 0x06004000 > +#define NETSPACE_V2_OE_HIGH 0x00000031 > +#define NETSPACE_V2_OE_VAL_LOW 0x10030000 > +#define NETSPACE_V2_OE_VAL_HIGH 0x00000000 > + > +#define NETSPACE_V2_GPIO_BUTTON 32 > + > +/* PHY related */ > +#define MV88E1116_LED_FCTRL_REG 10 > +#define MV88E1116_CPRSP_CR3_REG 21 > +#define MV88E1116_MAC_CTRL_REG 21 > +#define MV88E1116_PGADR_REG 22 > +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) > +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) > + > +#endif /* NETSPACE_V2_H */ > diff --git a/boards.cfg b/boards.cfg > index bc193c6..5bd320e 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -104,6 +104,9 @@ davinci_schmoogie arm arm926ejs > schmoogie davinci > davinci_sffsdr arm arm926ejs sffsdr > davinci davinci > davinci_sonata arm arm926ejs sonata > davinci davinci > suen3 arm arm926ejs km_arm > keymile kirkwood > +inetspace_v2 arm arm926ejs netspace_v2 > LaCie kirkwood netspace_v2:INETSPACE_V2 > +netspace_v2 arm arm926ejs netspace_v2 > LaCie kirkwood netspace_v2:NETSPACE_V2 > +netspace_max_v2 arm arm926ejs netspace_v2 > LaCie kirkwood netspace_v2:NETSPACE_MAX_V2 > guruplug arm arm926ejs - > Marvell kirkwood > mv88f6281gtw_ge arm arm926ejs - > Marvell kirkwood > openrd_base arm arm926ejs openrd > Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE > diff --git a/include/configs/netspace_v2.h b/include/configs/netspace_v2.h > new file mode 100644 > index 0000000..82a1233 > --- /dev/null > +++ b/include/configs/netspace_v2.h > @@ -0,0 +1,162 @@ > +/* > + * Copyright (C) 2011 Simon Guinot <sgui...@lacie.com> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#ifndef _CONFIG_NETSPACE_V2_H > +#define _CONFIG_NETSPACE_V2_H > + > +/* > + * Machine number definition > + */ > +#if defined(CONFIG_INETSPACE_V2) > +#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2 > +#define CONFIG_IDENT_STRING " IS v2" > +#elif defined(CONFIG_NETSPACE_V2) > +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 > +#define CONFIG_IDENT_STRING " NS v2" > +#elif defined(CONFIG_NETSPACE_MAX_V2) > +#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 > +#define CONFIG_IDENT_STRING " NS Max v2" > +#else > +#error "Unknown board" > +#endif > + > +/* > + * High Level Configuration Options (easy to change) > + */ > +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ > +#define CONFIG_KIRKWOOD /* SOC Family Name */ > +#define CONFIG_KW88F6281 /* SOC Name */ > +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ > + > +/* > + * Commands configuration > + */ > +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ > +#include <config_cmd_default.h> > +#define CONFIG_CMD_ENV > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_PING > +#define CONFIG_CMD_SF > +#define CONFIG_CMD_I2C > +#define CONFIG_CMD_IDE > +#define CONFIG_CMD_USB > + > +/* > + * Core clock definition. > + */ > +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ > + > +/* > + * mv-common.h should be defined after CMD configs since it used them > + * to enable certain macros > + */ > +#define CONFIG_NR_DRAM_BANKS 2 > +#include "mv-common.h" > + > +/* Remove or override few declarations from mv-common.h */ > +#undef CONFIG_RBTREE > +#undef CONFIG_ENV_SPI_MAX_HZ > +#undef CONFIG_SYS_IDE_MAXBUS > +#undef CONFIG_SYS_IDE_MAXDEVICE > +#undef CONFIG_SYS_PROMPT > +#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ > +#define CONFIG_SYS_IDE_MAXBUS 1 > +#define CONFIG_SYS_IDE_MAXDEVICE 1 > +#define CONFIG_SYS_PROMPT "ns2> " > + > +/* > + * Ethernet Driver configuration > + */ > +#ifdef CONFIG_CMD_NET > +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ > +#define CONFIG_NETCONSOLE > +#endif > + > +/* > + * SATA Driver configuration > + */ > +#ifdef CONFIG_MVSATA_IDE > +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET > +/* Network Space Max v2 use 2 SATA ports */ > +#ifdef CONFIG_NETSPACE_MAX_V2 > +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET > +#endif > +#endif > + > +/* > + * Enable GPI0 support > + */ > +#define CONFIG_KIRKWOOD_GPIO > + > +/* > + * File systems support > + */ > +#define CONFIG_CMD_EXT2 > +#define CONFIG_CMD_FAT > + > +/* > + * Use the HUSH parser > + */ > +#define CONFIG_SYS_HUSH_PARSER > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " > + > +/* > + * Console configuration > + */ > +#define CONFIG_CONSOLE_MUX > +#define CONFIG_SYS_CONSOLE_IS_IN_ENV > + > +/* > + * Enable device tree support > + */ > +#define CONFIG_OF_LIBFDT > + > +/* > + * Environment variables configurations > + */ > +#define CONFIG_ENV_IS_IN_SPI_FLASH > +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */ > +#define CONFIG_ENV_SIZE 0x1000 /* 4KB */ > +#define CONFIG_ENV_ADDR 0x70000 > +#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ > + > +/* > + * Default environment variables > + */ > +#define CONFIG_BOOTARGS "console=ttyS0,115200" > + > +#define CONFIG_BOOTCOMMAND \ > + "dhcp && run netconsole; " \ > + "if run usbload || run diskload; then bootm; fi" > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "stdin=serial\0" \ > + "stdout=serial\0" \ > + "stderr=serial\0" \ > + "bootfile=uImage\0" \ > + "loadaddr=0x800000\0" \ > + "autoload=no\0" \ > + "netconsole=" \ > + "set stdin $stdin,nc; " \ > + "set stdout $stdout,nc; " \ > + "set stderr $stderr,nc;\0" \ > + "diskload=ide reset && " \ > + "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ > + "usbload=usb start && " \ > + "fatload usb 0:1 $loadaddr /boot/$bootfile\0" > + > +#endif /* _CONFIG_NETSPACE_V2_H */ > -- > 1.7.5.1 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot
signature.asc
Description: Digital signature
_______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot