Current implementation of riscv_timer.c only assumes readable TIMER CSRs present (IOW, Zicntr extension is available). Core Local Interruptors (CLINT) found on T-Head C9xx cores expose its mtime register through TIME CSR directly instead of a MMIO register, thus is compatible with the driver.
As running in S-Mode isn't necessary for the driver to operate, Kconfig and comments are also adapted to avoid confusion. Reference: https://github.com/riscv-software-src/opensbi/commit/ca7810aecdba Signed-off-by: Yao Zi <[email protected]> --- This is necessary for several platforms based on T-Head C9xx to get system ticks, e.g. TH1520, K230 and CV1800. Tested on th1520-lichee-pi-4a in both M-mode and S-mode (with mainline OpenSBI). drivers/timer/Kconfig | 4 ++-- drivers/timer/riscv_timer.c | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index cb6fc0e7fda..00c4067a23b 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -241,8 +241,8 @@ config RISCV_TIMER bool "RISC-V timer support" depends on TIMER && RISCV help - Select this to enable support for a generic RISC-V S-Mode timer - driver. + Select this to enable support for a generic timer driver based + on RISC-V TIMER CSR. config ROCKCHIP_TIMER bool "Rockchip timer support" diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index 1f4980ceb38..3e6f0cd6d11 100644 --- a/drivers/timer/riscv_timer.c +++ b/drivers/timer/riscv_timer.c @@ -7,7 +7,7 @@ * * RISC-V architecturally-defined generic timer driver * - * This driver provides generic timer support for S-mode U-Boot. + * This driver provides generic timer support through TIME CSR for U-Boot. */ #include <config.h> @@ -106,6 +106,7 @@ static const struct timer_ops riscv_timer_ops = { static const struct udevice_id riscv_timer_ids[] = { { .compatible = "riscv,timer", }, + { .compatible = "thead,c900-clint" }, { } }; -- 2.48.1
