- Use DM based clock API - Switch to upstream style DSI panel bindings - improve ganged mode support - remove hardcoded Tegra 2 parts
--- Changes in v2 - ganged mode logic aligned with Linux DSI driver implementation - improved packed calculations - improved lane calculations - dropped unneeded changes --- Svyatoslav Ryhel (12): video: tegra20: dc: switch to newer clk API video: tegra20: dc: remove hardcoded Tegra 2 specific parts video: tegra20: dc: remove excessive headers video: tegra20: dc: improve code quality video: tegra20: dsi: check for panels among child nodes video: tegra20: dsi: switch to newer clk API video: tegra20: dsi: align ganged mode implementation video: tegra20: dsi: make SOL delay calculation mode independent video: tegra20: dsi: calculate packet parameters for video mode video: tegra20: dsi: calculate lanes for ganged mode video: tegra20: dsi: pass source on DSI configuration ARM: tegra: endeavoru: adjust panel node arch/arm/dts/tegra30-htc-endeavoru.dts | 23 +- .../include/asm/arch-tegra20/clock-tables.h | 2 + drivers/video/tegra20/tegra-dc.c | 104 ++++----- drivers/video/tegra20/tegra-dsi.c | 219 +++++++++++++----- 4 files changed, 215 insertions(+), 133 deletions(-) -- 2.43.0
