These helpers wrongly return the updated register value. As a non-zero
value indicates failure, this causes various clock operations are
considered failed.
Correct the return value to constant zero, since these simple MMIO
operations won't fail. This fixes clock enabling failures during booting
process,
In: serial@4140000
Out: serial@4140000
Err: serial@4140000
Net: Enable clock-controller@3002000 failed
failed to enable clock 0
No ethernet found.
which leads to misoperation of various peripherals.
Fixes: 5f364e072e7 ("clk: sophgo: cv1800b: Add clock controller driver for
cv1800b SoC")
Tested-by: Yuguo Pei <[email protected]>
Signed-off-by: Yao Zi <[email protected]>
---
drivers/clk/sophgo/clk-common.h | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sophgo/clk-common.h b/drivers/clk/sophgo/clk-common.h
index 95b82e968d0..a9e83d0d689 100644
--- a/drivers/clk/sophgo/clk-common.h
+++ b/drivers/clk/sophgo/clk-common.h
@@ -45,12 +45,14 @@ static inline u32 cv1800b_clk_getbit(void *base, struct
cv1800b_clk_regbit *bit)
static inline u32 cv1800b_clk_setbit(void *base, struct cv1800b_clk_regbit
*bit)
{
- return setbits_le32(base + bit->offset, BIT(bit->shift));
+ setbits_le32(base + bit->offset, BIT(bit->shift));
+ return 0;
}
static inline u32 cv1800b_clk_clrbit(void *base, struct cv1800b_clk_regbit
*bit)
{
- return clrbits_le32(base + bit->offset, BIT(bit->shift));
+ clrbits_le32(base + bit->offset, BIT(bit->shift));
+ return 0;
}
static inline u32 cv1800b_clk_getfield(void *base,
--
2.48.1
