> -----Original Message-----
> From: Ravulapalli, Naresh Kumar <[email protected]>
> Sent: Tuesday, March 4, 2025 1:07 PM
> To: [email protected]
> Cc: Marek Vasut <[email protected]>; Simon Goldschmidt
> <[email protected]>; Chee, Tien Fong
> <[email protected]>; Meng, Tingting <[email protected]>;
> Tom Rini <[email protected]>; Ng, Boon Khai <[email protected]>;
> Jit Loon Lim <[email protected]>; Alif Zakuan Yuslaimi
> <[email protected]>; Ravulapalli, Naresh Kumar
> <[email protected]>
> Subject: [PATCH 1/2] arch: arm: dts: Enable kernel itb file generation for
> Agilex5 SoCFPGA
>
> Load and entry addresses are corrected for Agilex5 SoCFPGA board which
> would enable to generate the kernel itb file with the right addresses.
>
> Signed-off-by: Naresh Kumar Ravulapalli
> <[email protected]>
> ---
> arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
> b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
> index 15306db600..93a8e0697d 100644
> --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
> @@ -106,8 +106,13 @@
> arch = "arm64";
> os = "linux";
> compression = "none";
> + #if
> IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
> + load = <0x86000000>;
> + entry = <0x86000000>;
> + #else
> load = <0x6000000>;
> entry = <0x6000000>;
> + #endif
> kernel_blob: blob-ext {
> filename = "Image";
> };
> --
> 2.35.3
Reviewed-by: Tien Fong Chee <[email protected]>
Best regards,
Tien Fong
