On 08/03/2025 14:54, Paul Barker wrote:
> On 05/03/2025 20:05, Marek Vasut wrote:
>> On 3/4/25 5:37 PM, Paul Barker wrote:
>>
>> [...]
>>
>>> +static int rzg2l_usbphy_ctrl_assert(struct reset_ctl *reset_ctl)
>>> +{
>>> + struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(reset_ctl->dev);
>>> + u32 val;
>>> +
>>> + val = readl(priv->regs + RESET);
>>> + val |= reset_ctl->id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
>>
>> u32 val = reset_ctl->id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
>>
>>> + /* If both ports are in reset, we can also place the PLL into reset. */
>>> + if ((val & PHY_RESET_MASK) == PHY_RESET_MASK)
>>> + val |= RESET_PLLRESET;
>>
>> setbits_le32(priv->regs + RESET, val);Reviewing this again before I send v2: We need to read the RESET register separately to determine whether to set the RESET_PLLRESET bit or not. Since we need the separate read, we may as well use writel() instead of setbits_le32(). >> >>> + writel(val, priv->regs + RESET); >>> + return 0; >>> +} Thanks, -- Paul Barker
OpenPGP_0x27F4B3459F002257.asc
Description: OpenPGP public key
OpenPGP_signature.asc
Description: OpenPGP digital signature
